US5179293A
Expired / Lapsed
US
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Bipolar output stage switching circuit
Assignee: Analog Devices Inc
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Filing: 1991-01-15
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Granted: 1993-01-12
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Expires: 2011-01-15
Abstract
Abstract A technique and circuit for switching a bipolar output stage between an active mode in which the stage operates as a voltage source and an inhibit mode in which the stage is deactivated and the output node presents a floating high-impedance. The output stage may be in a digital device such as a digital pin driver circuit, or in an analog amplifier. Considering first the digital application, in the active mode, a digital output is switched between logic high and logic low voltages established by external references. The logic high and logic low reference voltages, and the corresponding output voltages, may be set to zero, a positive voltage or a negative voltage independently of each other; a logic "one" can thus be set to a voltage below a logic "zero". When the output stage is an analog amplifier, in active mode it amplifies its input signal. In either arrangement, in the "inhibit mode", the output stage transistors are turned off by reverse-biasing their base-emitter junctions relative to the output node of the circuit, to provide a floating high-impedance output node. In the inhibit mode, additional means are provided for substantially cancelling leakage current at the output node.
Inventors
- 👤 E. Barry Hilton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826; H03K19/003; H03K19/00346; H03K19/00353
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
162 words
In a switching circuit for a bipolar output stage having complementary NPN and PNP transistors selectively operable in a first mode, called the "active" mode, for supplying an output voltage to an output node, and selectively operable in a second mode, called the "inhibit" mode, for providing at the output node an undriven, floating high impedance, the improvement comprising: a. means for receiving an INHIBIT command signal, to initiate inhibit mode operation; b. means operable in response to signals supplied by the means for receiving, for reverse biasing the base-emitter junctions of the complementary NPN and PNP transistors by only one pn junction voltage relative to the output node; and c. buffer means connected to the output node for supplying to the means for reverse biasing a buffered voltage corresponding to the voltage at the output node, and means associated with the buffer means for substantially canceling output leakage currents from the output node to the buffer means in the inhibit mode.
Claim 2
Dependent Claim
162 words
In a switching circuit for a bipolar output stage having complementary NPN and PNP transistors selectively operable in a first mode, called the "active" mode, for supplying an output voltage to an output node, and selectively operable in a second mode, called the "inhibit" mode, for providing at the output node an undriven, floating high impedance, the improvement comprising: a. means for receiving an INHIBIT command signal, to initiate inhibit mode operation; b. means operable in response to signals supplied by the means for receiving, for reverse biasing the base-emitter junctions of the complementary NPN and PNP transistors by only one pn junction voltage relative to the output node; and c. buffer means connected to the output node for supplying to the means for reverse biasing a buffered voltage corresponding to the voltage at the output node, and means associated with the buffer means for substantially canceling output leakage currents from the output node to the buffer means in the inhibit mode.
Claim 3
Dependent Claim
65 words
The apparatus of claim 1 wherein the buffer means comprises a pair of complementary NPN and PNP transistors having their bases connected together and connected to the output node such that the output node must supply the difference between their base currents, and wherein the means for substantially canceling the output leakage currents causes the base currents of th buffer transistors to be substantially equal.
Claim 4
Dependent Claim
145 words
A switching circuit for a bipolar output stage, comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means for receiving a first reference voltage; and d. first selective fixing means operatively connected to the bases of said transistors for selectively fixing the voltage at the output node at the first reference voltage in response to a data signal supplied in a first state, said first selective fixing mean including a first node operatively connected to the bases of said transistors which provides a high impedance when the voltage a the output is not substantially equal to the first reference voltage, and first current source means operatively connected to the first node for selectively supplying current to the first node.
Claim 5
Dependent Claim
145 words
A switching circuit for a bipolar output stage, comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means for receiving a first reference voltage; and d. first selective fixing means operatively connected to the bases of said transistors for selectively fixing the voltage at the output node at the first reference voltage in response to a data signal supplied in a first state, said first selective fixing mean including a first node operatively connected to the bases of said transistors which provides a high impedance when the voltage a the output is not substantially equal to the first reference voltage, and first current source means operatively connected to the first node for selectively supplying current to the first node.
Claim 6
Dependent Claim
101 words
A switching circuit as described in claim 3, further comprising: e. means for receiving a second reference voltage; and f. second selective fixing means operatively connected to the bases of said transistors for selectively fixing the voltage at the outlet node at the second reference voltage, said second selective fixing means including a second node operatively connected to the bases of said transistors which provides high impedance when the voltage at the output is not substantially equal to the second reference voltage, and second current source means operatively connected to the second node for selectively supplying current to the second node.
Claim 7
Dependent Claim
124 words
A switching circuit as described in claim 4, wherein said first node includes a first diode with a first electrode which is operatively connected to said first reference voltage and a second electrode which is operatively connected to the bases of said transistors, said fist current source means includes a transistor with a collector which is operatively connected to the first electrode of said first diode, said second node includes a second diode with a first electrode which is operatively connected to said second reference voltage and a second electrode which is operatively connected to the bases of said transistors, and said second current source means includes a transistor with a collector which is operatively connected to the first electrode of said second diode.
Claim 8
Dependent Claim
41 words
The circuit described in claim 4 further comprising: g. means selectively operable responsive to an inhibit signal for reverse biasing the base-emitter junction of each of said transistors by controlling the base voltages of said transistors relative to the output node.
Claim 9
Dependent Claim
118 words
A bipolar output switching circuit comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means of receiving first and a second reference voltages; means responsive to an input signal for selectively forward-biasing th base-emitter junctions of said transistor and for selectively controlling the base voltages of said transistors to selectively produce at the output one of said reference voltages; and e. means responsive to an inhibit signal or selectively reverse biasing the base-emitter junction of each of said transistors by controlling the base voltages of said transistors relative to the output node.
Claim 10
Dependent Claim
118 words
A bipolar output switching circuit comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means of receiving first and a second reference voltages; means responsive to an input signal for selectively forward-biasing th base-emitter junctions of said transistor and for selectively controlling the base voltages of said transistors to selectively produce at the output one of said reference voltages; and e. means responsive to an inhibit signal or selectively reverse biasing the base-emitter junction of each of said transistors by controlling the base voltages of said transistors relative to the output node.
Claim 11
Dependent Claim
168 words
A bipolar output stage selectively operable in a first mode, called the "active" mode, for supplying an output voltage to an output node, and selectively operable in a second mode, called the "inhibit" mode, for providing at the output node an undriven, floating high impedance, comprising: a. an output node; b. a par of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means for selectively forward biasing said transistors when the circuit is in active mode and for selectively controlling th base voltages of said transistors to produce an output voltage on the output node when the circuit si in active mode; d. means for selectively reverse-biasing the base-emitter junctions of said transistors when the circuit is in inhibit mode; and e. means, responsive to the voltage at the output node and the voltages on the bases of said transistors, for limiting the reverse-biased base-emitter junction voltages of said transistors.
Claim 12
Dependent Claim
168 words
A bipolar output stage selectively operable in a first mode, called the "active" mode, for supplying an output voltage to an output node, and selectively operable in a second mode, called the "inhibit" mode, for providing at the output node an undriven, floating high impedance, comprising: a. an output node; b. a par of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. means for selectively forward biasing said transistors when the circuit is in active mode and for selectively controlling th base voltages of said transistors to produce an output voltage on the output node when the circuit si in active mode; d. means for selectively reverse-biasing the base-emitter junctions of said transistors when the circuit is in inhibit mode; and e. means, responsive to the voltage at the output node and the voltages on the bases of said transistors, for limiting the reverse-biased base-emitter junction voltages of said transistors.
Claim 13
Dependent Claim
30 words
The circuit described in claim 8 wherein said means for limiting limits the reverse-biased base-emitter junction voltages of each of said transistors to only one forward biased pn junction voltage.
Claim 14
Dependent Claim
104 words
The circuit described in claim 8 wherein said means for limiting includes a buffer, having an input which is operatively connected to the output node, and having an output, and a first diode and a second diode, said first diode having a cathode which is operatively connected to the output of the buffer, said second diode having an anode which is operatively connected to the output of the buffer, said first diode having an anode which is operatively connected to the base of said NPN transistor, and said second diode having a cathode which is operatively connected to the base of said PNP transistor.
Claim 15
Dependent Claim
150 words
A bipolar output switching circuit with a buffer for sensing the output and means for limiting leakage current comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. a buffer for sensing the voltage at the output node, said buffere including a pair of complementary NPN and PNP transistor each having a base which is operatively connected to the output node, an emitter, and a collector; d. means for making the base currents of the buffere NPN and PNP transistors substantially equal, including 1. a first simulating transistors, having a base, an emitter and a collector, provided in correspondence with the buffere NPN transistor, 2. a second simulating transistor, having a base, and emitter and a collector, provided in correspondence with the buffer PNP transistor,
Claim 16
Dependent Claim
150 words
A bipolar output switching circuit with a buffer for sensing the output and means for limiting leakage current comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having a base and an emitter, each of said emitters operatively connected to the output node; c. a buffer for sensing the voltage at the output node, said buffere including a pair of complementary NPN and PNP transistor each having a base which is operatively connected to the output node, an emitter, and a collector; d. means for making the base currents of the buffere NPN and PNP transistors substantially equal, including 1. a first simulating transistors, having a base, an emitter and a collector, provided in correspondence with the buffere NPN transistor, 2. a second simulating transistor, having a base, and emitter and a collector, provided in correspondence with the buffer PNP transistor,
Claim 17
Dependent Claim
99 words
means for making the base currents of the first simulating transistor and the second simulating transistor substantially equal, 4. means for making the emitter currents of the buffere NPN transistor and the first simulating transistor substantially equal, 5. means for making the emitter currents of the buffere PNP transistor and the second simulating transistor substantially equal, 6. first matching means or making the collector-base voltages of the first simulating transistor and the buffere NPN transistor substantially equal, and 7. second matching means for making the collector-base voltages of the second simulating transistor and the buffer PNP transistor substantially equal.
Claim 18
Dependent Claim
99 words
means for making the base currents of the first simulating transistor and the second simulating transistor substantially equal, 4. means for making the emitter currents of the buffere NPN transistor and the first simulating transistor substantially equal, 5. means for making the emitter currents of the buffere PNP transistor and the second simulating transistor substantially equal, 6. first matching means or making the collector-base voltages of the first simulating transistor and the buffere NPN transistor substantially equal, and 7. second matching means for making the collector-base voltages of the second simulating transistor and the buffer PNP transistor substantially equal.
Claim 19
Dependent Claim
46 words
The circuit described in claim 11 wherein said first matching means fixes collector-base voltages of 0 on the first simulating transistor and the buffer NPN transistor, and said second matching means fixed collector-base voltages of 0 on the second simulating transistor and the buffer PNP transistor.
Claim 20
Dependent Claim
209 words
A bipolar output switching circuit with a buffer for sensing the output and means for limiting leakage current comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having base and an emitter, each of said emitters operatively connected to the output node; c. a buffere for sensing the voltage at the output node, said buffer including a first and a second transistor each having a base which is imperatively connected to the output node, an emitter, and a collector; d. means for making the base currents of the first and second transistors substantially equal, including 1. a first simulating transistor, having a base, one emitter, and a collector, provided in correspondence with the first transistor, 2. a second simulating transistor, having a base, an emitter, and a collector, provided in correspondence with the second transistor, 3. means for establishing an emitter current in said first simulating transistor identical to the emitter current in said first transistor, 4. means for establishing a base current in said second simulating transistor identical to the base current in said first simulating transistor, and 5. means for establishing an emitter current in said second transistor identical to the emitter current in said second simulating transistor.
Claim 21
Dependent Claim
209 words
A bipolar output switching circuit with a buffer for sensing the output and means for limiting leakage current comprising: a. an output node; b. a pair of complementary NPN and PNP transistors, each of said transistors having base and an emitter, each of said emitters operatively connected to the output node; c. a buffere for sensing the voltage at the output node, said buffer including a first and a second transistor each having a base which is imperatively connected to the output node, an emitter, and a collector; d. means for making the base currents of the first and second transistors substantially equal, including 1. a first simulating transistor, having a base, one emitter, and a collector, provided in correspondence with the first transistor, 2. a second simulating transistor, having a base, an emitter, and a collector, provided in correspondence with the second transistor, 3. means for establishing an emitter current in said first simulating transistor identical to the emitter current in said first transistor, 4. means for establishing a base current in said second simulating transistor identical to the base current in said first simulating transistor, and 5. means for establishing an emitter current in said second transistor identical to the emitter current in said second simulating transistor.
Claim 22
Dependent Claim
53 words
The circuit described in claim 13, said means for making base current substantially equal further including 6. means for making the collector-base voltages of the first simulating transistor and the first transistor substantially equal, and 7. means or making the collector-base voltages of the second simulating transistor and the second transistor substantially equal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |