High speed analog/digital driver

Claim 2

A driver comprising: input switching means, connected to a data select signal and to a plurality of analog input signals, for selecting a desired one of said analog input signals and applying said selected analog input signal as an output signal thereof, wherein said input switching means comprises a plurality of first switching bridges each having an input node, and an output node, each of said first switching bridges being responsive at its input node to a corresponding one of said analog input signals, and the output signal of said input switching means being responsive to a signal appearing at the output node of any of said first switching bridges, second switching means, having a second switching bridge connected in series with the output of said input switching means, wherein said second switching means is responsive to an enable signal for either selectively causing said second switching bridge to assume a conductive state and thereby route said selected analog input signal, appearing at the output of said input switching means, through said second switching bridge as an output signal thereof or selectively assume a non-conductive state; and a buffer, responsive to the output of said second switching bridge, for amplifying said selected analog signal appearing at the output of said second switching bridge and applying the resulting amplified signal as an output of said driver, or alternatively causing said driver output to assume a high-impedance state whenever said second switching bridge becomes non-conductive.

Claim 3

The driver in claim 1 wherein each of said first switching bridges has at least one switching node, and said driver further comprises first switching means, responsive to said data select signal, for applying a suitable signal to the switching node of each of said first switching bridges so as to forward-bias at least a selected one of said first bridges and route the analog input signal appearing at the input node thereof through said selected bridge to the output of said input switching means.

Claim 4

The driver in claim 2 wherein the first switching means comprises a current mode switch inter-connected to a complementary current mode switch each of which is also connected to an opposite switching node of each of said first switching bridges.

Claim 5

The driver in claim 3 wherein the first switching means further comprises a current mirror, connected to said current mode switch, and a complementary current mirror, connected both to said complementary current mode switch and also to said current mirror, for supplying switching current to said current mode switch and to said complementary current mode switch, respectively.

Claim 6

The driver in claim 4 further comprising a voltage controlled current reference, responsive to the value of an appropriate analog control voltage applied to said driver and connected to said current mirror, for setting the magnitude of the switching current and thereby determining transition time of said driver output.

Claim 7

The driver in claim 2 wherein said second switching bridge has an input node connected to the output of said input switching means, at least one switching node and an output, and wherein said second switching means, comprises means, responsive to said enable signal, for applying an appropriate signal to the switching node of the second switching bridge so as to selectively forward bias said second switching bridge and thereby route said selected analog input signal therethrough to said buffer or alternatively to selectively reverse-bias said second switching bridge so as to cause the output of the driver to assume a high impedance state.

Claim 8

The driver in claim 6 wherein the second switching means comprises a second current mode switch inter-connected to a second complementary current mode switch each of which is also connected to an opposite switching node of each of said second switching bridge.

Claim 9

The driver in claim 7 wherein the second switching means further comprises a second current mirror, connected to said second current mode switch, and a second complementary current mirror, connected both to said second complementary current mode switch and also to said second current mirror, for supplying switching current to said second current mode switch and to said second complementary current mode switch, respectively.

Claim 10

The driver in claim 8 further comprising a current reference, connected to said second current mirror, for setting the magnitude of the switching current flowing in said second current mirror and in said second complementary current mirror to a value which minimizes the switching speed of said second bridge.

Claim 11

The driver in claim 1 wherein said buffer comprises: means, responsive to output current generated by the driver, for protecting the buffer from overload output currents; means, responsive to said output current, for protecting the buffer from excessively sharp impulse currents, and means, responsive to the voltage appearing at the output of the driver, for protecting the buffer from high voltages applied thereto.

Claim 12

A driver comprising: input switching means, connected to a data select signal and to a plurality of analog input signals, for selecting a desired one of said analog input signals and applying said selected analog input signal as an output signal thereof, wherein said input switching means comprises a plurality of first switching bridges each having an input node, an output node and at least one switching node, each of said first switching bridges being responsive at its input node to a corresponding one of said analog input signals, and the output signal of said input switching means being responsive to a signal appearing at the output node of any of said first switching bridges; first switching means, responsive to said data select signal, for applying a suitable signal to the switching node of each of said first switching bridges so as to forwardbias at least a selected one of said first bridges and route the analog input signal appearing at the input node thereof through said selected bridge to the output of said input switching means; second switching means, responsive to an enable signal, for applying an appropriate signal to the switching node of a second switching bridge so as to selectively forward or reverse bias said second switching bridge; said second switching bridge having at least one switching node, an output and an input node connected to the output of said input switching means, and being responsive to said second switching means, for either selectively assuming a forward-biased state and thereby routing said selected analog input signal, appearing at the output of said input switching means, through said second switching bridge as an output signal thereof or selectively assuming a reverse-biased state; and a buffer, responsive to the output of said second switching bridge, for amplifying said selected analog signal appearing at the output of said second switching bridge and applying the resulting amplified signal as an output of said driver, or alternatively causing said driver output to assume a high-impedance state whenever said second switching bridge is reverse-biased.

Claim 13

A driver comprising: input switching means, connected to a data select signal and to a plurality of analog input signals, for selecting a desired one of said analog input signals and applying said selected analog input signal as an output signal thereof, wherein said input switching means comprises a plurality of first switching bridges each having an input node, an output node and at least one switching node, each of said first switching bridges being responsive at its input node to a corresponding one of said analog input signals, and the output signal of said input switching means being responsive to a signal appearing at the output node of any of said first switching bridges; first switching means, responsive to said data select signal, for applying a suitable signal to the switching node of each of said first switching bridges so as to forwardbias at least a selected one of said first bridges and route the analog input signal appearing at the input node thereof through said selected bridge to the output of said input switching means; second switching means, responsive to an enable signal, for applying an appropriate signal to the switching node of a second switching bridge so as to selectively forward or reverse bias said second switching bridge; said second switching bridge having at least one switching node, an output and an input node connected to the output of said input switching means, and being responsive to said second switching means, for either selectively assuming a forward-biased state and thereby routing said selected analog input signal, appearing at the output of said input switching means, through said second switching bridge as an output signal thereof or selectively assuming a reverse-biased state; and a buffer, responsive to the output of said second switching bridge, for amplifying said selected analog signal appearing at the output of said second switching bridge and applying the resulting amplified signal as an output of said driver, or alternatively causing said driver output to assume a high-impedance state whenever said second switching bridge is reverse-biased.

Claim 14

The driver in claim 11 wherein the first switching means comprises a curent mode switch inter-connected to a complementary current mode switch each of which is also connected to an opposite switching node of each of said first switching bridges.

Claim 15

The driver in claim 12 wherein the first switching means further comprises a current mirror, connected to said current mode switch, and a complementary current mirror, connected both to said complementary current mode switch and also to said current mirror, for supplying switching current to said current mode switch and to said complementary current mode switch, respectively.

Claim 16

The driver in claim 13 further comprising a voltage controlled current reference, responsive to the value of an appropriate analog control voltage applied to said driver and connected to said current mirror, for setting the magnitude of the switching current and thereby determining transition time of said driver.

Claim 17

The driver in claim 11 wherein the second switching means comprises a second current mode switch inter-connected to a second complementary current mode switch each of which is also connected to an opposite switching node of each of said second switching bridge.

Claim 18

The driver in claim 15 wherein the second switching means further comprises a second current mirror, connected to said second current mode switch, and a second complementary current mirror, connected both to said second complementary current mode switch and also to said second current mirror, for supplying switching current to said second current mode switch and to said second complementary current mode switch, respectively.

Claim 19

The driver in claim 16 further comprising a current reference, connected to said second current mirror, for setting the magnitude of the switching current flowing in said second current mirror and in said second complementary current mirror to a value which minimizes the switching speed of said second bridge.

Claim 20

The driver in claim 11 wherein said buffer comprises: means, responsive to output current generated by the driver, for protecting the buffer from overload output currents; means, responsive to said output current, for protecting the buffer from excessively sharp impulse currents, and means, responsive to the voltage appearing at the output of the driver, for protecting the buffer from high voltages applied thereto.