Patent US5175705A successfully refreshed from Google Patents.
US5175705A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having circuit for prevention of overcharge of column line
Assignee: Toshiba Corp
•
Filing: 1990-06-22
•
Granted: 1992-12-29
•
Expires: 2010-06-22
Abstract
Abstract A semiconductor memory device comprises row lines, memory cells selectively driven by the row lines, and a column line connected to the memory cells. A load transistor is connected to the column line. A source/drain current path of a first transistor is connected between the column line and the load transistor. The gate potential of the first transistor is controlled by an output of an inverter. An input of the inverter is connected to the column line. A discharge circuit is also connected to the column line. When the potential on the column line is above a predetermined potential, the column line is discharged by the discharge circuit until the potential on the column line becomes equal to the predetermiend potential. For the predetermined potential, a potential obtained by subtracting the threshold voltage of the first transistor from the gate voltage thereof, may be used. By employing the construction described above, there is provided a semiconductor memory device having a mechanism for the prevention of an overcharge operation of the column line.
Inventors
- 👤 Hiroshi Iwahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 10:44
CPC Classifications
G; G11; G11C; G11C17/00; G11C7/00; G11C7/12; G11C16/00; G11C16/02; G11C16/06; G11C16/26
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
160 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: row lines; memory cells selectively driven by said row lines; a column line connected to said memory cells; a first transistor (15; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being connected to said column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor and a power supply terminal; and discharge means, connected to said column line, for discharging said column line, said discharge means being operative to discharge said column line to a predetermined critical potential when the potential on said column line is higher than said predetermined critical potential.
Claim 2
Dependent Claim
160 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: row lines; memory cells selectively driven by said row lines; a column line connected to said memory cells; a first transistor (15; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being connected to said column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor and a power supply terminal; and discharge means, connected to said column line, for discharging said column line, said discharge means being operative to discharge said column line to a predetermined critical potential when the potential on said column line is higher than said predetermined critical potential.
Claim 3
Dependent Claim
26 words
A device as set forth in claim 1, wherein each of said memory cells comprises an electrically programmable metal-oxide semiconductor (MOS) transistor having a floating gate.
Claim 4
Dependent Claim
35 words
A device as set forth in claim 1, wherein said predetermined critical potential is a value equal to a gate potential of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 5
Dependent Claim
75 words
A device as set forth in claim 1, wherein said discharge means includes inverting means, said inverting means having an input and an output, the input of said inverting means being connected to said column line, the output of said inverting means being connected to the gate of said first transistor (15; 15A), for controlling the potential on the gate of said first transistor (15; 15A) in response to the potential on said column line.
Claim 6
Dependent Claim
27 words
A device as set forth in claim 4, wherein said inverting means is a complementary metal-oxide semiconductor (CMOS) inverter comprising a P-channel transistor and an N-channel transistor.
Claim 7
Dependent Claim
61 words
A device as set forth in claim 4, further comprising an additional transistor (12), said additional transistor having a drain-source current path and a gate, said drain-source current path of said additional transistor being connected between a power supply terminal and said column line, the gate of said additional transistor (12) being connected to the gate of said first transistor (15).
Claim 8
Dependent Claim
69 words
A device as set forth in claim 1, wherein said discharge means includes a second transistor (23, 23A; 26), conduction of said second transistor (23; 23A; 26) being controlled in response to the potential on said column line, said column line being discharged through said second transistor (23; 23A; 26) to said predetermined critical potential when the potential on said column line is higher than said predetermined critical potential.
Claim 9
Dependent Claim
37 words
A device as set forth in claim 7, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 10
Dependent Claim
24 words
A device as set forth in claim 7, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 11
Dependent Claim
92 words
A device as set forth in claim 7, wherein said second transistor (23; 23A; 26) has a drain-source current path, said drain-source current path of said second transistor (23; 23A; 26) being connected between said column line and a circuit node, a potential on said circuit node varying in response to the potential on said column line, said column line being discharged through said current path of said second transistor (23; 23A; 26) to said predetermined critical potential when the potential on said column line is higher than said predetermined critical potential.
Claim 12
Dependent Claim
37 words
A device as set forth in claim 10, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 13
Dependent Claim
24 words
A device as set forth in claim 10, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 14
Dependent Claim
40 words
A device as set forth in claim 10, wherein when the potential on said column line rises, the potential on said circuit node falls, while when the potential on said column lines falls, the potential on said circuit node rises.
Claim 15
Dependent Claim
24 words
A device as set forth in claim 13, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 16
Dependent Claim
37 words
A device as set forth in claim 13, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 17
Dependent Claim
44 words
A device as set forth in claim 13, wherein the gate of said first transistor (15A) is connected to said circuit node, said circuit node controlling the potential on the gate of said first transistor in response to the potential on said column line.
Claim 18
Dependent Claim
25 words
A device as set forth in claim 16, wherein threshold voltages of said first and second transistors (15A, 26) are equal to substantially zero volts.
Claim 19
Dependent Claim
24 words
A device as set forth in claim 16, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 20
Dependent Claim
37 words
A device as set forth in claim 16, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 21
Dependent Claim
99 words
A device as set forth in claim 13, wherein said discharge means further includes a third transistor (21) and a fourth transistor (22; 22A) connected in series between said power supply terminal and ground, wherein said circuit node is a junction of said third and fourth transistors, and wherein a gate potential of said third transistor (21) is controlled in response to the potential on said column line, whereby when the potential on said column line rises, the potential on said circuit node falls, while when the potential on column line falls, the potential on said circuit node rises.
Claim 22
Dependent Claim
28 words
A device as set forth in claim 20, wherein a threshold voltage of said third transistor (21) is equal to a threshold voltage of said first transistor (15).
Claim 23
Dependent Claim
21 words
A device as set forth in claim 20, wherein a threshold voltage of said second transistor (23) is approximately zero volts.
Claim 24
Dependent Claim
26 words
A device as set forth in claim 20, wherein said fourth transistor (22A) is a depletion type transistor having a gate connected to the source thereof.
Claim 25
Dependent Claim
33 words
A device as set forth in claim 20, wherein said third transistor (21) has a gate, the gate of said third transistor (21) being connected to the gate of said first transistor (15).
Claim 26
Dependent Claim
24 words
A device as set forth in claim 20, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 27
Dependent Claim
37 words
A device as set forth in claim 20, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 28
Dependent Claim
48 words
A device as set forth in claim 20, wherein said discharge means further comprises potential drop means connected in series with said third and fourth transistors, said potential drop means being connected between said circuit node and one end of a drain-source current path of said third transistor.
Claim 29
Dependent Claim
24 words
A device as set forth in claim 27, wherein each of said memory cells comprises an electrically programmable MOS transistor having a floating gate.
Claim 30
Dependent Claim
37 words
A device as set forth in claim 27, wherein said predetermined critical potential is a value equal to a potential on the gate of said first transistor (15, 15A) minus a threshold voltage of said first transistor.
Claim 31
Dependent Claim
189 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: a plurality of row lines; a plurality of memory cells selectively driven by said row lines; a plurality of column lines connected to said memory cells; column select means (61 to 6m) for selecting one of said column lines; a first transistor (16; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being coupled to a selected column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said selected column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor (15; 15A) and a power supply terminal; and discharge means, coupled to said selected column line, for discharging said selected column line, said discharge means being operative to discharge said selected column line to a predetermined critical potential when the potential on said selected column line is higher than said predetermined critical potential.
Claim 32
Dependent Claim
189 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: a plurality of row lines; a plurality of memory cells selectively driven by said row lines; a plurality of column lines connected to said memory cells; column select means (61 to 6m) for selecting one of said column lines; a first transistor (16; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being coupled to a selected column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said selected column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor (15; 15A) and a power supply terminal; and discharge means, coupled to said selected column line, for discharging said selected column line, said discharge means being operative to discharge said selected column line to a predetermined critical potential when the potential on said selected column line is higher than said predetermined critical potential.
Claim 33
Dependent Claim
202 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: a plurality of row lines; a plurality of memory cells selectively driven by said row lines; a plurality of column lines connected to said memory cells; column select means (61 to 6m) for selecting one of said column lines; a first transistor (15; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being coupled to a selected column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said selected column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor (15; 15A) and a power supply terminal; and a plurality of discharge means for discharging said selected column line, each of said discharge means being coupled to a corresponding one of the column lines and being operative to discharge the corresponding one of the column lines to a predetermined critical potential when the potential on said selected column line is higher than said predetermined critical potential.
Claim 34
Dependent Claim
202 words
A semiconductor memory device having a circuit for prevention of an overcharge operation of a column line, comprising: a plurality of row lines; a plurality of memory cells selectively driven by said row lines; a plurality of column lines connected to said memory cells; column select means (61 to 6m) for selecting one of said column lines; a first transistor (15; 15A) having a drain-source current path and a gate, one end of said drain-source current path of said first transistor (15; 15A) being coupled to a selected column line, a potential on the gate of said first transistor (15; 15A) being controlled in response to a potential on said selected column line; a load transistor (16) having a drain-source current path connected between the other end of said drain-source current path of said first transistor (15; 15A) and a power supply terminal; and a plurality of discharge means for discharging said selected column line, each of said discharge means being coupled to a corresponding one of the column lines and being operative to discharge the corresponding one of the column lines to a predetermined critical potential when the potential on said selected column line is higher than said predetermined critical potential.
References Cited (Backward Citations)
US4417328A
Cited
US4542485A
Cited
JPS58185094A
Cited
JPS5977700A
Cited
JPS60136996A
Cited
US4694429A
Cited
US4769784A
Cited
US4797856A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-29 | 1996-06-29 | 1996-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-29 | 2000-06-29 | 2000-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-29 | 2004-06-29 | 2004-12-29 | $7700.00 | Window Closed / Lapsed |