Semiconductor storage device

Claim 1

A semiconductor device comprising: a memory cell array including a plurality of memory cells each having a floating gate arranged in a row and a column direction; a plurality of column lines for connecting said memory cells in the column direction; a plurality of row lines for connecting said memory cells in the row direction; a column decoder for receiving a first address signal related to said column direction; a column selector for selecting said column lines, said column selector being driven by outputs from said column decoder; a row decoder for receiving a second address signal related to said row direction and selecting said row lines; a voltage dividing circuit connected between a write voltage terminal and ground; a sense amplifier for reading the data stored in the memory cells; and at least one write circuit for applying a high voltage to one column line selected from said plurality of column lines in accordance with a write data, said high voltage being supplied from said write voltage terminal, when writing for one memory cell selected from said plurality of memory cells, said write circuit comprising a first MOSFET having a first conductivity type and a second MOSFET having a second conductivity type opposite to said first conductivity type connected in series between said write voltage terminal and said column selector in which said first MOSFET turns on when a reference voltage is applied to its gate electrode in accordance with said write data, and said second MOSFET turns on when an output voltage from said voltage dividing circuit is applied to its gate electrode.