Patent US5173618A successfully refreshed from Google Patents.
US5173618A
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Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew
Assignee: Philips Semiconductors Inc
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Filing: 1990-05-14
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Granted: 1992-12-22
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Expires: 2010-05-14
Abstract
Abstract A clock generator for producing a pair of nonoverlapping clock signals. In one embodiment, a flip-flop functions as a state machine to clock a pair of complementary switches that direct successive pulses of a clock signal alternately to one and then the other of a pair of output clock signal ports. In another embodiment, each of a pair of output clock signals is generated by an AND gate having a first input connected directly to a clock input and having a second input connected through a delay element. Mechanisms are included to sense the amount of delay introduced by this delay element and to select a new delay value when the sensed delay is outside of an operating range.
Inventors
- 👤 Robert E. Eisenstadt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
109 words
A clock generator comprising: a D-type flip-flop having a clock input, a D input and an inverting output, said D input being connected to said inverting output; a first buffer having a signal input connected to the clock input of the D-type flip-flop, having an inverting enable input connected to the output of the D-type flip-flop and having an output at which a first output clock signal is produced; a second buffer having an input connected to the clock input of the D-type flip-flop, having an enable input connected to the output of the D-type flip-flop and having an output at which a second output clock signal is produced.
Claim 2
Dependent Claim
109 words
A clock generator comprising: a D-type flip-flop having a clock input, a D input and an inverting output, said D input being connected to said inverting output; a first buffer having a signal input connected to the clock input of the D-type flip-flop, having an inverting enable input connected to the output of the D-type flip-flop and having an output at which a first output clock signal is produced; a second buffer having an input connected to the clock input of the D-type flip-flop, having an enable input connected to the output of the D-type flip-flop and having an output at which a second output clock signal is produced.
Claim 3
Dependent Claim
34 words
A clock generator as in claim 1 further comprising: a first repeater cell connected to the output of the first buffer; and a second repeater cell connected to the output of the second buffer.
Claim 4
Dependent Claim
30 words
A clock generator as in claim 1 further comprising: an inverting buffer connected between the clock input of the D-type flip-flop and the inputs of said first and second buffers.
Claim 5
Dependent Claim
30 words
A clock generator as in claim 3 further comprising: a third buffer connected between the output of the D-type flip-flop and the enable inputs of the first and second buffers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-22 | 1996-06-22 | 1996-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-22 | 2000-06-22 | 2000-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-22 | 2004-06-22 | 2004-12-22 | $7700.00 | Window Closed / Lapsed |