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US5172199A
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Compact nonvolatile semiconductor memory device using stacked active and passive elements
Assignee: Sharp Corp
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Filing: 1991-06-06
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Granted: 1992-12-15
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Expires: 2011-06-06
Abstract
Abstract A nonvolatile semiconductor memory device including a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode stacked on the gate region via a first dielectric film, and a second gate electrode stacked on the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions.
Inventors
- 👤 Yoshimitsu Yamauchi
- 👤 Kenichi Tanaka
- 👤 Keizo Sakiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10B; H10B69/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
88 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode formed on the gate region via a first dielectric film, a second gate electrode stacked upon the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions, and the second dielectric film having a lower breakdown voltage than said first dielectric film.
Claim 2
Dependent Claim
88 words
A nonvolatile semiconductor memory device comprising: a semiconductor substrate, a pair of impurity diffusion regions provided in the substrate, a gate region provided between the pair of impurity diffusion regions, a first gate electrode formed on the gate region via a first dielectric film, a second gate electrode stacked upon the first gate electrode via a second dielectric film, the first gate electrode being electrically short-circuited to one of the impurity diffusion regions, and the second dielectric film having a lower breakdown voltage than said first dielectric film.
Claim 3
Dependent Claim
21 words
A device as in claim 1, wherein the first gate electrode and the second gate electrode are each formed of polysilicon.
Claim 4
Dependent Claim
33 words
A device as in claim 1, wherein the first dielectric film is formed of SiO 2 , while the second dielectric film is formed of SiN or SiO 2 or SiO 2 SiN.
Claim 5
Dependent Claim
73 words
A nonvolatile integrated circuit semiconductor memory comprising an array of memory cells, each said memory cell comprising: an active device comprising a MOSFET constructed to have a first breakdown voltage, and a passive device comprising a capacitor constructed within approximately the same integrated circuit footprint area as said active device, said passive device using at least one insulating layer having a second breakdown voltage which is substantially less than said first breakdown voltage.
Claim 6
Dependent Claim
73 words
A nonvolatile integrated circuit semiconductor memory comprising an array of memory cells, each said memory cell comprising: an active device comprising a MOSFET constructed to have a first breakdown voltage, and a passive device comprising a capacitor constructed within approximately the same integrated circuit footprint area as said active device, said passive device using at least one insulating layer having a second breakdown voltage which is substantially less than said first breakdown voltage.
Claim 7
Dependent Claim
107 words
A nonvolatile integrated circuit semiconductor memory comprising an array of memory cells, each said memory cell comprising: an active device constructed to have a first breakdown voltage, a passive device constructed within approximately the same integrated circuit footprint area as said active device, said passive device using at least one insulating layer having a second breakdown voltage which is substantially less than said first breakdown voltage, and wherein said active device comprises a MOSFET having a gate insulation layer of a first thickness and said passive device comprises a capacitor disposed directly above said MOSFET and having an inter-electrode insulation layer less than half said first thickness.
Claim 8
Dependent Claim
107 words
A nonvolatile integrated circuit semiconductor memory comprising an array of memory cells, each said memory cell comprising: an active device constructed to have a first breakdown voltage, a passive device constructed within approximately the same integrated circuit footprint area as said active device, said passive device using at least one insulating layer having a second breakdown voltage which is substantially less than said first breakdown voltage, and wherein said active device comprises a MOSFET having a gate insulation layer of a first thickness and said passive device comprises a capacitor disposed directly above said MOSFET and having an inter-electrode insulation layer less than half said first thickness.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |