Patent US5693551A successfully refreshed from Google Patents.
← Back to Patent Explorer
JPH0240960A Expired / Lapsed JP ⏱️ 0.0 years remaining

Input protecting circuit device

Assignee: NEC Corp
•
Filing: 1988-07-30
•
Granted: —
•
Expires: 2008-07-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To reduce an occupied area and prevent dielectric breakdown of a pad lower layer by constituting a MOS transistor and a diode constituting an input protecting circuit device, in a region almost directly under the pad. CONSTITUTION:On a P-type semiconductor substrate, a pad 2 is formed of a metal layer like aluminum. At a position directly under the pad 2, an N-type impurity layer 5 and an N-type impurity layer 6 are formed. The layer is adjacent to the impurity layer 5 and a part of the layer 6 is arranged directly under the pad 2. By the pad 2 and the impurity layers 5, 6, a MOS transistor(TR) 22 is formed in which the pad, the layer 5 and the layer 6 are used as a gate, a drain and a source, respectively. By the impurity layer 5 and the the substrate 1, a diode (D) 23 is constituted directly under the pad 2. The gate and the source of TR 22 and the cathode of D 23 are connected with the pad 22 and a first stage circuit, and the drain and the anode are grounded, thereby forming a circuit. Hence, an occupied area is reduced and dielectric breakdown of the pad lower layer can be prevented.

Inventors

  • 👤 Hitoshi Mitani
  • 👤 三谷 仁

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:39
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS6236867A Cited
JPS63291470A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag