Five-volt tolerant differential receiver

Claim 2

A differential receiver comprising: a. first and second transistors coupled in parallel to a data input; b. third and fourth transistors coupled in parallel to a reference voltage input line; c. a fifth transistor coupling the first, second, third, and fourth transistors to ground; d. a sixth transistor coupling the first transistor to a voltage supply; e. a seventh transistor for coupling the first and second transistors to a data output; and f. an eighth transistor coupling the data input to the data output.

Claim 3

The differential receiver of claim 1 wherein the transistors are field effect transistors.

Claim 4

The differential receiver of claim 1 wherein the sixth and seventh transistors are P-channel field effect transistors and the remaining transistors are N-channel field effect transistors.

Claim 5

The differential receiver of claim 2 wherein the gate width of the second transistor is small in relation to the gate width of the first transistor.

Claim 8

A differential amplifier comprising: a. a biasing power supply; b. a reference voltage source; c. a first transistor coupleable to an input logic signal; d. a second transistor in parallel with the first transistor, the drain of the second transistor coupled to the biasing power supply; e. a third transistor in parallel with the first transistor, the drain of the third transistor coupled to the biasing power supply and the source of the third transistor coupled to an output node; f. a fourth transistor coupling the drain of the first transistor to the biasing power supply; g. a fifth transistor coupled to the reference voltage source, the drain of the fifth transistor coupled to the output node; h. a sixth transistor in parallel with the fifth transistor, the drain of the sixth transistor coupled to the biasing power supply; i. a seventh transistor coupling the sources of the first, second, fifth, and sixth transistors to ground; and j. an eighth transistor coupled at its gate to the drain of the first transistor, at its drain to the biasing power supply, and at its source to the output node.

Claim 9

A differential amplifier comprising: a. a biasing power supply; b. a reference voltage source; c. a first transistor coupleable to an input logic signal; d. a second transistor in parallel with the first transistor, the drain of the second transistor coupled to the biasing power supply; e. a third transistor in parallel with the first transistor, the drain of the third transistor coupled to the biasing power supply and the source of the third transistor coupled to an output node; f. a fourth transistor coupling the drain of the first transistor to the biasing power supply; g. a fifth transistor coupled to the reference voltage source, the drain of the fifth transistor coupled to the output node; h. a sixth transistor in parallel with the fifth transistor, the drain of the sixth transistor coupled to the biasing power supply; i. a seventh transistor coupling the sources of the first, second, fifth, and sixth transistors to ground; and j. an eighth transistor coupled at its gate to the drain of the first transistor, at its drain to the biasing power supply, and at its source to the output node.

Claim 10

The differential amplifier of claim 6 wherein the fourth and eighth transistors are P-channel field effect transistors and the remaining transistors are N-channel field effect transistors.

Claim 11

The differential receiver of claim 6 wherein the gate width of the second transistor is small in relation to the gate width of the first transistor.

Claim 12

The differential receiver of claim 6 wherein the gate width of the sixth transistor is small in relation to the gate width of the fifth transistor.

Claim 13

A differential circuit comprising: first and second input transistors, each having a source-to-drain path and a gate, the gate of the first transistor being connected to a second input, the source-to-drain paths of the first and second transistors being each connected at one end to a common node, the other end of the source-to-drain path of the second transistor being connected to an output; third and fourth output transistors, each having a source-to-drain path and a gate, the source-to-drain paths of the third and fourth transistors being separately connected from the other ends of said source-to-drain paths of said first and second transistors and a first supply terminal, said other end of the source-to-drain path of said first transistor being connected to the gates of the third and fourth transistors; a fifth transistor having a source-to-drain path connecting said common node to a second supply terminal and having a gate connected to said gates of said third and fourth transistors; and a sixth transistor having a source-to-drain path connected between said first supply terminal and said output, and having a gate connected to said input.

Claim 14

A differential circuit comprising: first and second input transistors, each having a source-to-drain path and a gate, the gate of the first transistor being connected to a second input, the source-to-drain paths of the first and second transistors being each connected at one end to a common node, the other end of the source-to-drain path of the second transistor being connected to an output; third and fourth output transistors, each having a source-to-drain path and a gate, the source-to-drain paths of the third and fourth transistors being separately connected from the other ends of said source-to-drain paths of said first and second transistors and a first supply terminal, said other end of the source-to-drain path of said first transistor being connected to the gates of the third and fourth transistors; a fifth transistor having a source-to-drain path connecting said common node to a second supply terminal and having a gate connected to said gates of said third and fourth transistors; and a sixth transistor having a source-to-drain path connected between said first supply terminal and said output, and having a gate connected to said input.

Claim 15

A circuit according to claim 10 wherein said first and second transistors are N-channel and said third and fourth transistors are P-channel.

Claim 16

A circuit according to claim 10 wherein said second input is a reference input.

Claim 17

A circuit according to claim 10 including seventh and eighth transistors, each having a source-to-drain path connected between said common node and said first supply terminal, the seventh transistor having a gate connected to said first input, said eighth transistor having a gate connected to said second input.

Claim 18

A circuit according to claim 13 wherein said first, second, fifth, sixth, seventh and eighth transistors are N-channel, and said third and fourth transistors are P-channel.

Claim 19

A circuit according to claim 14 wherein said first supply terminal is connected to a positive voltage and said second supply terminal is connected to ground.

Claim 20

A circuit according to claim 15 wherein said second input is a reference voltage.