US5170131A
Expired / Lapsed
US
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Demodulator for demodulating digital signal modulated by minimum shift keying and method therefor
Assignee: Sharp Corp
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Filing: 1991-11-04
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Granted: 1992-12-08
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Expires: 2011-11-04
Abstract
Abstract Disclosed is a demodulation circuit for demodulating a modulated signal obtained by minimum shift keying. The demodulation circuit includes two synchronous detection circuits for detecting the modulated signal synchronously with two signals having the phases different from each other by 90°, respectively, a circuit for discriminating the amplitude of the output signal of one of the synchronous detection circuits to convert the output signal into a rectangular wave having two logical levels, and a circuit for sampling the rectangular wave signal in synchronization with a clock signal having a frequency corresponding to one-bit duration of the digital data. Both of two signals having the phases different by 90° from each other, all of which are necessary for the synchronous detection, and the clock signal are generated based on a signal (Vt (θ)) obtained by multiplying the output signal of the one of the synchronous detection circuits and the output signal of the other of the synchronous detection circuits.
Inventors
- 👤 Chihara Takahiro
- 👤 Miyazaki Masao
- 👤 Ohta Tomozo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 14:22
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/0014; H04L2027/0016; H04L2027/0024; H04L2027/0044; H04L2027/0046; H04L2027/0048
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
250 words
A demodulation device for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means includes: first phase shifting means for shifting the phase of said generated clock signal by 90°, amplitude discriminating means for outputting a signal of a first logical level when the amplitude of the output signal of said first detecting means is within a predetermined range and outputting a signal of a second logical level when said amplitude is out of said predetermined range, and sampling means responsive to the clock signal having the phase shifted by said first phase shifting means for sampling the output signal of said amplitude discriminating means.
Claim 2
Dependent Claim
250 words
A demodulation device for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means includes: first phase shifting means for shifting the phase of said generated clock signal by 90°, amplitude discriminating means for outputting a signal of a first logical level when the amplitude of the output signal of said first detecting means is within a predetermined range and outputting a signal of a second logical level when said amplitude is out of said predetermined range, and sampling means responsive to the clock signal having the phase shifted by said first phase shifting means for sampling the output signal of said amplitude discriminating means.
Claim 3
Dependent Claim
70 words
The demodulation device according to claim 1, wherein said clock signal generating means includes: first oscillator means having a variable output frequency, third detecting means responsive to the output of said multiplying means for detecting the phase of the output signal of said first oscillator means, and first controlling means responsive to the output signal of said third detecting means for controlling the output frequency of said first oscillator means.
Claim 4
Dependent Claim
66 words
The demodulation device according to claim 2, further comprising: second controlling means responsive to the output of said multiplying means for generating a control signal, second oscillator means for generating said first signal having a frequency corresponding to said control signal, and second phase shifting means for shifting the phase of the output signal of said second oscillator means by 90° to generate said second signal.
Claim 5
Dependent Claim
54 words
The demodulation device according to claim 3, wherein said digital data includes first and second logical values, said modulated signal has a first frequency and a second frequency respectively corresponding to said first and second logical values, and the center frequency of the output signal of said second oscillator means is said first frequency.
Claim 6
Dependent Claim
57 words
The demodulation device according to claim 1, wherein said digital data is differentially coded in advance, and said reproducing means further includes: means for delaying said sampled signal by a time period equivalent to said one-bit duration, and means for producing an exclusive OR signal of the output signal of said delaying means and said sampled signal.
Claim 7
Dependent Claim
198 words
A demodulation device for demodulating a modulated signal obtained by modulating differentially coded digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means further includes: means for delaying said sampled signal by a time period equivalent to said one-bit duration, and means for generating an exclusive OR signal of the output signal of said delaying means and said sampled signal.
Claim 8
Dependent Claim
198 words
A demodulation device for demodulating a modulated signal obtained by modulating differentially coded digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means further includes: means for delaying said sampled signal by a time period equivalent to said one-bit duration, and means for generating an exclusive OR signal of the output signal of said delaying means and said sampled signal.
Claim 9
Dependent Claim
239 words
A demodulation device for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means includes: amplitude discriminating means for outputting a signal of a first logical level when the amplitude of the output signal of said first detecting means is within a predetermined range and outputting a signal of a second logical level when said amplitude is out of said predetermined range, and means for shifting the phase of the output signal of said amplitude discriminating means by 90° and sampling said signal having the phase shifted in response to said generated clock signal.
Claim 10
Dependent Claim
239 words
A demodulation device for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, comprising: first detecting means for detecting said modulated signal synchronously with a first signal, second detecting means for detecting said modulated signal synchronously with a second signal, the phase of said first signal and the phase of said second signal differing from each other by 90°, multiplying means for multiplying the output of said first detecting means by the output of said second detecting means, clock signal generating means responsive to the multiplication output of said multiplying means for generating a clock signal having a phase synchronized with that of said signal component, and means responsive to the clock signal generated by said clock signal generating means for reproducing said digital data from the output of said first detecting means, wherein said reproducing means includes: amplitude discriminating means for outputting a signal of a first logical level when the amplitude of the output signal of said first detecting means is within a predetermined range and outputting a signal of a second logical level when said amplitude is out of said predetermined range, and means for shifting the phase of the output signal of said amplitude discriminating means by 90° and sampling said signal having the phase shifted in response to said generated clock signal.
Claim 11
Dependent Claim
70 words
The demodulation device according to claim 7, wherein said clock signal generating means includes: first oscillator means having a variable output frequency, third detecting means responsive to the output of said multiplying means for detecting the phase of the output signal of said first oscillator means, and first controlling means responsive to the output signal of said third detecting means for controlling the output frequency of said first oscillator means.
Claim 12
Dependent Claim
66 words
The demodulation device according to claim 8, further comprising: second controlling means responsive to the output of said multiplying means for generating a control signal, second oscillator means for generating said first signal having a frequency corresponding to said control signal, and second phase shifting means for shifting the phase of the output signal of said second oscillator means by 90° to generate said second signal.
Claim 13
Dependent Claim
54 words
The demodulation device according to claim 9, wherein said digital data includes first and second logical values, said modulated signal has a first frequency and a second frequency respectively corresponding to said first and second logical values, and the center frequency of the output signal of said second oscillator means is said first frequency.
Claim 14
Independent Claim
193 words
A method for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, said method comprising the steps of: detecting said modulated signal synchronously with a first signal, detecting said modulated signal synchronously with a second signal having a phase different by 90° from the phase of said first signal, multiplying said signal detected synchronously with the first signal by said signal detected synchronously with the second signal, generating a clock signal having the phase synchronized with said signal component in response to said multiplied signal, and reproducing said digital data from said signal detected synchronously with the first signal in response to said generated clock signal, said reproducing step comprising the steps of: shifting the phase of said generated clock signal by 90°, converting said signal detected synchronously with the first signal into a signal having a logical level varying corresponding to the change of the amplitude of said signal detected synchronously with the first signal, and sampling said converted signal in response to said clock signal having the phase shifted.
Claim 15
Independent Claim
193 words
A method for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, said method comprising the steps of: detecting said modulated signal synchronously with a first signal, detecting said modulated signal synchronously with a second signal having a phase different by 90° from the phase of said first signal, multiplying said signal detected synchronously with the first signal by said signal detected synchronously with the second signal, generating a clock signal having the phase synchronized with said signal component in response to said multiplied signal, and reproducing said digital data from said signal detected synchronously with the first signal in response to said generated clock signal, said reproducing step comprising the steps of: shifting the phase of said generated clock signal by 90°, converting said signal detected synchronously with the first signal into a signal having a logical level varying corresponding to the change of the amplitude of said signal detected synchronously with the first signal, and sampling said converted signal in response to said clock signal having the phase shifted.
Claim 16
Independent Claim
192 words
A method for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, said method comprising the steps of: detecting said modulated signal synchronously with a first signal, detecting said modulated signal synchronously with a second signal having a phase different by 90° from the phase of said first signal, multiplying said signal detected synchronously with the first signal by said signal detected synchronously with the second signal, generating a clock signal having the phase synchronized with said signal component in response to said multiplied signal, and reproducing said digital data from said signal detected synchronously with the first signal in response to said generated clock signal, said reproducing step comprising the steps of: converting said signal detected synchronously with the first signal into a signal having a logical level varying corresponding to the change of the amplitude of said signal detected synchronously with the first signal, shifting the phase of said converted signal by 90°, and sampling said signal having the phase shifted in response to said generated clock signal.
Claim 17
Independent Claim
192 words
A method for demodulating a modulated signal obtained by modulating digital data by minimum shift keying, said modulated signal including a signal component having a frequency corresponding to one-bit duration of said digital data, said method comprising the steps of: detecting said modulated signal synchronously with a first signal, detecting said modulated signal synchronously with a second signal having a phase different by 90° from the phase of said first signal, multiplying said signal detected synchronously with the first signal by said signal detected synchronously with the second signal, generating a clock signal having the phase synchronized with said signal component in response to said multiplied signal, and reproducing said digital data from said signal detected synchronously with the first signal in response to said generated clock signal, said reproducing step comprising the steps of: converting said signal detected synchronously with the first signal into a signal having a logical level varying corresponding to the change of the amplitude of said signal detected synchronously with the first signal, shifting the phase of said converted signal by 90°, and sampling said signal having the phase shifted in response to said generated clock signal.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |