Patent US1822123A successfully refreshed from Google Patents.
Patent US5168182A successfully refreshed from Google Patents.
US5168182A
Expired / Lapsed
US
⏱️ 0.0 years remaining
0-100% duty cycle, transformer isolated fet driver
Assignee: RTX Corp
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Filing: 1991-06-24
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Granted: 1992-12-01
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Expires: 2011-06-24
Abstract
Abstract A transformer isolates a control circuit from a FET, the control circuit including a clock generator for providing, when enabled, a clock signal to the transformer primary. A PWM input selectively disables the clock generator from providing the clock signal to the transformer primary. The transformer secondary is connected in a full wave centertap configuration for providing a full wave rectified version of the clock signal, the full wave rectified version being a relatively constant DC voltage signal supplied at one level to the FET to turn on the FET when the clock generator is enabled to provide the clock signal to the primary. The centertap configuration provides a relatively constant DC voltage signal at a second level to the FET to turn off the FET when the clock generator is disabled by the PWM input from providing the clock signal to the primary.
Inventors
- 👤 David C. Salerno
- 👤 Walter O. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:05
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/689; H03K17/691; H03K17/60; H03K17/605; H03K17/61
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
265 words
Apparatus, comprising: control means, for providing a repetitive time varying clock signal having a selected frequency, and for providing a disable signal having binary logic states; clock means, responsive to said clock signal and said disable signal, for providing a pair of square wave signals on a corresponding pair of signal lines when said disable signal is at a first one of said binary logic states, said pair of square wave signals being in an inverse phase relationship to each other, and for providing on each one of said corresponding pair of signal lines a constant DC voltage signal when said disable signal is at a second one of said binary logic states; a transformer, having a primary winding and a secondary winding, a first one of said corresponding pair of signal lines being coupled to one end of said primary winding, a second one of said corresponding pair of signal lines being coupled to a second end of said primary winding; full wave rectifier means, connected to said transformer secondary winding, for rectifying said pair of square wave signals and for providing as a result of said rectifying a rectified DC voltage signal at a first level, and for providing said rectified DC voltage signal at a second level when said disable signal is at said second one of said binary logic states; and transistor means, for conducting electrical current therethrough when said rectified DC voltage signal is at said first DC voltage level, and for not conducting electrical current therethrough when said rectified DC voltage signal is at said second DC voltage level.
Claim 2
Dependent Claim
265 words
Apparatus, comprising: control means, for providing a repetitive time varying clock signal having a selected frequency, and for providing a disable signal having binary logic states; clock means, responsive to said clock signal and said disable signal, for providing a pair of square wave signals on a corresponding pair of signal lines when said disable signal is at a first one of said binary logic states, said pair of square wave signals being in an inverse phase relationship to each other, and for providing on each one of said corresponding pair of signal lines a constant DC voltage signal when said disable signal is at a second one of said binary logic states; a transformer, having a primary winding and a secondary winding, a first one of said corresponding pair of signal lines being coupled to one end of said primary winding, a second one of said corresponding pair of signal lines being coupled to a second end of said primary winding; full wave rectifier means, connected to said transformer secondary winding, for rectifying said pair of square wave signals and for providing as a result of said rectifying a rectified DC voltage signal at a first level, and for providing said rectified DC voltage signal at a second level when said disable signal is at said second one of said binary logic states; and transistor means, for conducting electrical current therethrough when said rectified DC voltage signal is at said first DC voltage level, and for not conducting electrical current therethrough when said rectified DC voltage signal is at said second DC voltage level.
Claim 3
Dependent Claim
44 words
The apparatus of claim 1, further comprising: buffer means, connected between said corresponding pair of signal lines and said ends of said transformer primary, for amplifying the current level of said pair of square wave signals and said pair of constant DC voltage signals.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1, wherein said transistor means comprises a Metal Oxide Semiconductor Field Effect Transistor device.
Claim 5
Dependent Claim
15 words
The apparatus of claim 1, wherein said transistor means comprises a Field Effect Transistor device.
Claim 6
Dependent Claim
14 words
The apparatus of claim 1, wherein said transistor means comprises a bipolar transistor device.
Claim 7
Dependent Claim
106 words
The apparatus of claim 1, wherein said full wave rectifier means comprises a pair of diodes, an anode terminal of a first one of said pair of diodes being connected to a first end of said transformer secondary winding, a cathode terminal of said first one of said pair of diodes being connected to a first terminal of said transistor means, an anode terminal of a second one of said pair of diodes being connected to a second end of said transformer secondary winding, a cathode terminal of said second one of said pair of diodes being connected to said first terminal of said transistor means.
Claim 8
Dependent Claim
14 words
The apparatus of claim 1, wherein said clock signal comprises a square wave signal.
Claim 9
Dependent Claim
19 words
The apparatus of claim 1, wherein said clock means comprises a pair of flip-flops responsive to said clock signal.
Claim 10
Dependent Claim
240 words
Apparatus for isolating a control circuit from a power device, the apparatus allowing for turn-on/turn-off operation of the power device in the full range of from 0 to 100%, the apparatus comprising: means for providing a pair of square wave signals on a corresponding pair of signal lines when a disable signal is at a first binary logic state, said pair of square wave signals being in an inverse phase relationship to each other, and for providing on each one of said corresponding pair of signal lines a constant DC voltage level when said disable signal is at a second binary logic state; a transformer, having a primary winding and a secondary winding, a first one of said corresponding pair of signal lines being coupled to one end of said primary winding, a second one of said corresponding pair of signal lines being coupled to a second end of said primary winding; and full wave rectifier means, connected to said transformer secondary winding, for rectifying said pair of square wave signals and for providing a constant DC voltage signal at a first DC voltage level to turn on the power device for conducting electrical current therethrough, and for providing said constant DC voltage signal at a second DC voltage level when said disable signal is at said second one of said binary logic states to turn off the power device to prevent the power device from conducting electrical current therethrough.
Claim 11
Dependent Claim
240 words
Apparatus for isolating a control circuit from a power device, the apparatus allowing for turn-on/turn-off operation of the power device in the full range of from 0 to 100%, the apparatus comprising: means for providing a pair of square wave signals on a corresponding pair of signal lines when a disable signal is at a first binary logic state, said pair of square wave signals being in an inverse phase relationship to each other, and for providing on each one of said corresponding pair of signal lines a constant DC voltage level when said disable signal is at a second binary logic state; a transformer, having a primary winding and a secondary winding, a first one of said corresponding pair of signal lines being coupled to one end of said primary winding, a second one of said corresponding pair of signal lines being coupled to a second end of said primary winding; and full wave rectifier means, connected to said transformer secondary winding, for rectifying said pair of square wave signals and for providing a constant DC voltage signal at a first DC voltage level to turn on the power device for conducting electrical current therethrough, and for providing said constant DC voltage signal at a second DC voltage level when said disable signal is at said second one of said binary logic states to turn off the power device to prevent the power device from conducting electrical current therethrough.
Claim 12
Dependent Claim
44 words
The apparatus of claim 9, further comprising: buffer means, connected between said corresponding pair of signal lines and said ends of said transformer primary, for amplifying the current level of said pair of square wave signals and said pair of constant DC voltage levels.
Claim 13
Dependent Claim
106 words
The apparatus of claim 9, wherein said full wave rectifier means comprises a pair of diodes, an anode terminal of a first one of said pair of diodes being connected to a first end of said transformer secondary winding, a cathode terminal of said first one of said pair of diodes being connected to a first terminal of said transistor means, an anode terminal of a second one of said pair of diodes being connected to a second end of said transformer secondary winding, a cathode terminal of said second one of said pair of diodes being connected to said first terminal of said transistor means.
Claim 14
Dependent Claim
21 words
The apparatus of claim 9, wherein said means for providing a pair of square wave signals comprises a pair of flip-flops.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-01 | 1996-06-01 | 1996-12-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-01 | 2000-06-01 | 2000-12-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-01 | 2004-06-01 | 2004-12-01 | $7700.00 | Window Closed / Lapsed |