US4471422A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dc-to-ac Inverter
Assignee: YORK-LITE ELECTRONICS Inc
•
Filing: 1981-01-09
•
Granted: 1984-09-11
•
Expires: 2001-01-09
Abstract
Abstract A dc-to-ac inverter employing a control low power section and a power section. The low power section comprises a square wave generator, cross-coupled NOR latches and low level transistor switches for providing switching current to the power section. The power section employs complementary FET drivers and power switches connected to a battery or other source of dc and a ferro-resonant transformer for changing dc to ac. The power section is protected by a voltage sensor. In a preferred embodiment, this voltage is proportional to the current through the respective power switches and is used to unlatch the applicable NOR latch, thereby causing shut off of the protected network of the power section.
Inventors
- 👤 Alton G. Hierholzer, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:50
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/42; H02M7/44; H02M7/48; H02M7/53; H02M7/537; H02M7/5383; H02M7/53846; H02M7/53862; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
238 words
A dc-to-ac inverter, comprising a square wave generator for generating a square wave having complementary square wave outputs, first and second latches connected respectively to said complementary square wave outputs, first and second low power switching transistors activated respectively by the outputs of said first and second latches, first and second power switch drives activated respectively by said first and second low power switching transistors, first and second electronic power switches connectable to a dc source and activated respectively by said first and second drivers into saturation, alternate phase high output voltages occurring as said power switches respectively come out of saturation preliminary to failing, a ferro-resonant transformer connected to the outputs of said first and second power switches for producing an ac output, said first and second latches respectively activating said low power switching transistors during the low portion of the respective square wave outputs as long as said respective output from power switches is below a predetermined voltage level, a voltage level in excess of said predetermined voltage level causing said respective latch to deactivate said respective low power switching transistor, said first and second latches including cross-coupled NOR gates, and a delayed input circuit for each of said first and second latches for insuring proper initial activation of said respective low power switching transistor, and a low voltage switch for deactivating said first and second low power switching transistors without deactivating said square wave generator.
Claim 2
Dependent Claim
238 words
A dc-to-ac inverter, comprising a square wave generator for generating a square wave having complementary square wave outputs, first and second latches connected respectively to said complementary square wave outputs, first and second low power switching transistors activated respectively by the outputs of said first and second latches, first and second power switch drives activated respectively by said first and second low power switching transistors, first and second electronic power switches connectable to a dc source and activated respectively by said first and second drivers into saturation, alternate phase high output voltages occurring as said power switches respectively come out of saturation preliminary to failing, a ferro-resonant transformer connected to the outputs of said first and second power switches for producing an ac output, said first and second latches respectively activating said low power switching transistors during the low portion of the respective square wave outputs as long as said respective output from power switches is below a predetermined voltage level, a voltage level in excess of said predetermined voltage level causing said respective latch to deactivate said respective low power switching transistor, said first and second latches including cross-coupled NOR gates, and a delayed input circuit for each of said first and second latches for insuring proper initial activation of said respective low power switching transistor, and a low voltage switch for deactivating said first and second low power switching transistors without deactivating said square wave generator.
Claim 3
Dependent Claim
207 words
A dc-to-ac electronic inverter, comprising a square wave generator for generating a square wave having complementary square wave outputs, first and second latches connected respectively to said complementary square wave outputs, first and second low power, switching transistors activated respectively by the outputs of said first and second latches, first and second power switch drivers activated respectively by said first and second low power switching transistors, first and second electronic power switches connectable to a dc source and activated respectively by said first and second drivers into saturation, the current therethrough being less than a predetermined value under normal load and internal operating conditions, and a ferro-resonant transformer connected to the outputs of said first and second power switches for producing an ac output, said first and second latches respectively activating said low power switching transistor during the low portion of the respective square wave outputs as long as the respective current through said power switches is below a predetermined current level causing said respective latch to deactivate said respective low power switching transistor, said first and second latches including cross-coupled NOR gates, and a delayed input circuit for each of said first and second latches for ensuring proper initial activation of said low power switching transistors.
Claim 4
Dependent Claim
207 words
A dc-to-ac electronic inverter, comprising a square wave generator for generating a square wave having complementary square wave outputs, first and second latches connected respectively to said complementary square wave outputs, first and second low power, switching transistors activated respectively by the outputs of said first and second latches, first and second power switch drivers activated respectively by said first and second low power switching transistors, first and second electronic power switches connectable to a dc source and activated respectively by said first and second drivers into saturation, the current therethrough being less than a predetermined value under normal load and internal operating conditions, and a ferro-resonant transformer connected to the outputs of said first and second power switches for producing an ac output, said first and second latches respectively activating said low power switching transistor during the low portion of the respective square wave outputs as long as the respective current through said power switches is below a predetermined current level causing said respective latch to deactivate said respective low power switching transistor, said first and second latches including cross-coupled NOR gates, and a delayed input circuit for each of said first and second latches for ensuring proper initial activation of said low power switching transistors.
References Cited (Backward Citations)
US3735235A
Cited
GB1501403A
Cited
US4013935A
Cited
US3946301A
Cited
US4079444A
Cited
US4149233A
Cited
US4150424A
Cited
EP0012547A1
Cited
JPS55147978A
Cited
US4293902A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-11 | 1988-03-12 | 1988-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-11 | 1992-03-12 | 1992-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-11 | 1996-03-12 | 1996-09-11 | $7700.00 | Window Closed / Lapsed |