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US5166604A
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Methods and apparatus for facilitating scan testing of asynchronous logic circuitry
Assignee: Altera Corp
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Filing: 1990-11-13
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Granted: 1992-11-24
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Expires: 2010-11-13
Abstract
Abstract Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.
Inventors
- 👤 Bahram Ahanin
- 👤 Craig S. Lytle
- 👤 Ricky W. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:32
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/31707
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
Apparatus for facilitating testing of logic circuitry which includes storage register means having at least one asynchronous input selected from the group consisting of a preset input, a clock input, and a clear input, said asynchronous input being normally supplied with a first input signal produced by first logic circuit means, said apparatus comprising: means for selectively inhibiting application of said first input signal to said asynchronous input when said logic circuitry is to be tested, wherein said means for selectively inhibiting is controlled by a control signal; means for selectively storing an applied test control input signal and for producing an output signal indicative of the stored signal, said output signal being said control signal; and means for enabling said means for selectively storing in order to store said test control input signal when said logic circuitry is to be tested, wherein said logic circuitry includes at least one normal data signal input terminal, wherein the signal applied to said input terminal may be stored in said storage register means during normal operation of said logic circuitry, and wherein the signal applied to said input terminal is also used as said test control input signal.
Claim 2
Dependent Claim
196 words
Apparatus for facilitating testing of logic circuitry which includes storage register means having at least one asynchronous input selected from the group consisting of a preset input, a clock input, and a clear input, said asynchronous input being normally supplied with a first input signal produced by first logic circuit means, said apparatus comprising: means for selectively inhibiting application of said first input signal to said asynchronous input when said logic circuitry is to be tested, wherein said means for selectively inhibiting is controlled by a control signal; means for selectively storing an applied test control input signal and for producing an output signal indicative of the stored signal, said output signal being said control signal; and means for enabling said means for selectively storing in order to store said test control input signal when said logic circuitry is to be tested, wherein said logic circuitry includes at least one normal data signal input terminal, wherein the signal applied to said input terminal may be stored in said storage register means during normal operation of said logic circuitry, and wherein the signal applied to said input terminal is also used as said test control input signal.
Claim 3
Dependent Claim
35 words
The apparatus defined in claim 1 wherein said means for selectively inhibiting comprises: means for selectively applying a signal having a predetermined logical value to said asynchronous input in lieu of said first input signal.
Claim 4
Dependent Claim
30 words
The apparatus defined in claim 1 wherein said means for selectively inhibiting comprises: controllable gate means interposed in circuit relationship between said first logic circuit means and said asynchronous input.
Claim 5
Dependent Claim
33 words
The apparatus defined in claim 3 wherein said controllable gate means logically combines said first input signal with a control signal so that said control signal can selectively override said first input signal.
Claim 6
Dependent Claim
63 words
The apparatus defined in claim 1 wherein said asynchronous input must be switchable both during normal operation of said logic circuitry and during testing of said logic circuitry, and wherein said means for selectively inhibiting comprises: a source of a test switching signal; and means for selectively applying said test switching signal to said asynchronous input in lieu of said first input signal.
Claim 7
Dependent Claim
14 words
The apparatus defined in claim 5 wherein said asynchronous input is said clock input.
Claim 8
Dependent Claim
26 words
The apparatus defined in claim 1 wherein said apparatus further comprises: means for clearing the stored signal when said logic circuitry is no longer being tested.
Claim 9
Dependent Claim
174 words
Apparatus for facilitating testing of logic circuitry which includes storage register means having at least one asynchronous input selected from the group consisting of a present input, a clock input, and a clear input, said asynchronous input being normally supplied with a first input signal produced by first logic circuit means, said apparatus comprising: means for selectively inhibiting application of said first input signal to said asynchronous input when said logic circuitry is to be tested; an output terminal; and means for applying said first input signal to said output terminal when said logic circuitry is to be tested, wherein said means for applying comprises: data storage means for storing data applied to a data input terminal and applying the stored data to said output terminal; and means for connecting said first input signal to said data input terminal when said logic circuitry is to be tested, such that said first input signal may be observed when said logic circuitry is to be tested by connecting said output terminal to an existing scan chain.
Claim 10
Dependent Claim
174 words
Apparatus for facilitating testing of logic circuitry which includes storage register means having at least one asynchronous input selected from the group consisting of a present input, a clock input, and a clear input, said asynchronous input being normally supplied with a first input signal produced by first logic circuit means, said apparatus comprising: means for selectively inhibiting application of said first input signal to said asynchronous input when said logic circuitry is to be tested; an output terminal; and means for applying said first input signal to said output terminal when said logic circuitry is to be tested, wherein said means for applying comprises: data storage means for storing data applied to a data input terminal and applying the stored data to said output terminal; and means for connecting said first input signal to said data input terminal when said logic circuitry is to be tested, such that said first input signal may be observed when said logic circuitry is to be tested by connecting said output terminal to an existing scan chain.
Claim 11
Dependent Claim
65 words
The apparatus defined in claim 8 wherein a scan clock signal is employed during testing of said logic circuitry, wherein said data storage means has a clock input terminal and stores data applied to said data input terminal in response to the application of a clock signal to said clock input terminal, and wherein said scan clock signal is applied to said clock input terminal.
Claim 12
Dependent Claim
57 words
The apparatus defined in claim 8 wherein said first input signal is one of a plurality of signals which are inhibited from application to said storage register means during testing of said logic circuitry, and wherein said means for connecting comprises: means for selectively applying any one of said plurality of signals to said data input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |