US5166546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit for generating a reset signal
Assignee: Qimonda AG
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Filing: 1992-01-22
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Granted: 1992-11-24
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Expires: 2012-01-22
Abstract
Abstract An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.
Inventors
- 👤 Dominique Savignac
- 👤 Dieter Gleis
- 👤 Brian Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:07
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
201 words
An integrated circuit for generating a reset signal, comprising: terminals for a first and a second supply potential; a serial RC network connected between said terminals, said RC network having an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between said components; an initializing circuit being connected parallel to said RC network, said initializing circuit having an output forming a second circuit node of the integrated circuit for providing a potential having a maximum value in response to the first supply potential; an inverter circuit connected between said first circuit node and said terminal for the second supply potential for providing supply voltage for said inverter circuit, said inverter circuit having an input connected to said second circuit node and an output forming a third circuit node of the integrated circuit; a transistor having a source-to-drain path connected between said second circuit node and said terminal for the second supply potential and having a gate connected to said third circuit node; and an additional inverter having an input at said third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.
Claim 2
Dependent Claim
201 words
An integrated circuit for generating a reset signal, comprising: terminals for a first and a second supply potential; a serial RC network connected between said terminals, said RC network having an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between said components; an initializing circuit being connected parallel to said RC network, said initializing circuit having an output forming a second circuit node of the integrated circuit for providing a potential having a maximum value in response to the first supply potential; an inverter circuit connected between said first circuit node and said terminal for the second supply potential for providing supply voltage for said inverter circuit, said inverter circuit having an input connected to said second circuit node and an output forming a third circuit node of the integrated circuit; a transistor having a source-to-drain path connected between said second circuit node and said terminal for the second supply potential and having a gate connected to said third circuit node; and an additional inverter having an input at said third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.
Claim 3
Dependent Claim
18 words
The integrated circuit according to claim 1, including a delay circuit connected downstream of said fourth circuit node.
Claim 4
Dependent Claim
31 words
The integrated circuit according to claim 1, wherein said initializing circuit includes at least one ohmic resistor connected between said terminal for the first supply voltage and said second circuit node.
Claim 5
Dependent Claim
66 words
The integrated circuit according to claim 3, wherein said transistor is a first transistor of a first conduction type, said initializing circuit includes a second transistor of a second conduction type opposite the first conduction type, said second transistor is connected between said at least one ohmic resistor and said second circuit node, and said second transistor has a gate connected to said third circuit node.
Claim 6
Dependent Claim
90 words
The integrated circuit according to claim 1, wherein said transistor has a first conduction type, and said initializing circuit includes two transistors of a second conduction type opposite the first conduction type, said two transistors having source-to-drain paths connected in series with one another between said terminal for the first supply potential and said second circuit node, one of said two transistors having a gate connected to said terminal for the second supply potential, and the other of said two transistors having a gate connected to said third circuit node.
Claim 7
Dependent Claim
97 words
The integrated circuit according to claim 3, wherein said transistor has a first conduction type, and said initializing circuit includes two transistors of a second conduction type opposite the first conduction type, said two transistors having source-to-drain paths connected in series with one another between said terminal for the first supply potential and said second circuit node and in series with the ohmic resistor, one of said two transistors having a gate connected to said terminal for the second supply potential, and the other of said two transistors having a gate connected to said third circuit node.
Claim 8
Dependent Claim
28 words
The integrated circuit according to claim 1, wherein said initializing circuit includes a diode connected between said second circuit node and said terminal for the second supply potential.
Claim 9
Dependent Claim
31 words
The integrated circuit according to claim 1, wherein said initializing circuit includes at least two series-connected diodes connected between said second circuit node and said terminal for the second supply potential.
Claim 10
Dependent Claim
20 words
The integrated circuit according to claim 7, wherein said diode is an MOS transistor having an interconnected gate and drain.
Claim 11
Dependent Claim
24 words
The integrated circuit according to claim 8, wherein said diodes are MOS transistors, and each respective MOS transistor has an interconnected gate and drain.
Claim 12
Dependent Claim
25 words
The integrated circuit according to claim 1, wherein said inverter circuit includes at least one CMOS inverter having one p-channel transistor and one n-channel transistor.
Claim 13
Dependent Claim
20 words
The integrated circuit according to claim 11, wherein said p-channel transistor has a substrate connected to said first circuit node.
Claim 14
Dependent Claim
26 words
The integrated circuit according to claim 11, wherein said p-channel transistor has a substrate connected through a high-impedance to said terminal for the first supply potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |