IC tester

Claim 2

An IC tester for simultaneously testing a plurality of IC's, each IC having at least one first terminal and at least one second terminal said IC tester comprising: a common timing generating circuit which is common to a plurality of IC's to be tested for generating a common timing signal and transmitting the common timing signal to the second terminals of the plurality of IC's; a plurality of dedicated timing generating circuits corresponding to the plurality of IC's to be tested, each dedicated timing generating circuit generating an independent timing signal and transmitting the independent timing signal to a first terminal of the corresponding IC; control means for operating the plurality of IC's with an identical operational timing by controlling said common timing generating circuit and said plurality of dedicated timing generating circuits so as to enable said IC's to be tested simultaneously.

Claim 3

An IC tester for simultaneously testing a plurality of IC's, each IC including a first input terminal and a first output terminal as well as a second input terminal and a second output terminal, said IC tester comprising: a plurality of drivers respectively connected to respective first and second input terminals of a plurality of IC's to be tested which supply testing signals to the first and second input terminals; a plurality of comparators which are respectively connected to respective first and second output terminals of the plurality of IC's to be tested and which make a judgment on output signals emitted through the first and second output terminals; a common clock circuit which is common to the plurality of IC's to be tested for generating a common clock signal and transmitting the common clock signal to the drivers connected to the second input terminals of the IC's; a common strobing circuit which is common to the plurality of IC's to be tested for generating a common judgement timing signal and transmitting the common judgement timing signal to the comparators connected to the second output terminals of the IC's; a plurality of dedicated clock circuits corresponding to the plurality of IC's to be tested, each dedicated clock circuit generating an independent clock signal and transmitting the independent signal to the drivers connected to the first input terminals of the IC's; a plurality of dedicated strobing circuits corresponding to the plurality of IC's to be tested, each dedicated strobing circuits generating an independent judgement timing signal and transmitting the independent judgement timing signal to the comparators connected to the first output terminals of the IC's; and control means for operating the plurality of IC's with an identical operational timing by controlling said drivers, said comparators, said common clock circuit, said common strobing circuit, and dedicated clock circuits and said dedicated strobing circuits so as to enable said IC's to be tested simultaneously.

Claim 4

An IC tester for simultaneously testing a plurality of IC's, each IC including a first input terminal and a first output terminal as well as a second input terminal and a second output terminal, said IC tester comprising: a plurality of drivers respectively connected to respective first and second input terminals of a plurality of IC's to be tested which supply testing signals to the first and second input terminals; a plurality of comparators which are respectively connected to respective first and second output terminals of the plurality of IC's to be tested and which make a judgment on output signals emitted through the first and second output terminals; a common clock circuit which is common to the plurality of IC's to be tested for generating a common clock signal and transmitting the common clock signal to the drivers connected to the second input terminals of the IC's; a common strobing circuit which is common to the plurality of IC's to be tested for generating a common judgement timing signal and transmitting the common judgement timing signal to the comparators connected to the second output terminals of the IC's; a plurality of dedicated clock circuits corresponding to the plurality of IC's to be tested, each dedicated clock circuit generating an independent clock signal and transmitting the independent signal to the drivers connected to the first input terminals of the IC's; a plurality of dedicated strobing circuits corresponding to the plurality of IC's to be tested, each dedicated strobing circuits generating an independent judgement timing signal and transmitting the independent judgement timing signal to the comparators connected to the first output terminals of the IC's; and control means for operating the plurality of IC's with an identical operational timing by controlling said drivers, said comparators, said common clock circuit, said common strobing circuit, and dedicated clock circuits and said dedicated strobing circuits so as to enable said IC's to be tested simultaneously.