US5025205A
Expired / Lapsed
US
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Reconfigurable architecture for logic test system
Assignee: Texas Instruments Inc
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Filing: 1989-06-22
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Granted: 1991-06-18
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Expires: 2009-06-22
Abstract
Abstract A reconfigurable resource architecture enhances a test system's utilization by allowing product-mix dependent allocation of test system resources. The test system resources can be configured to test several device types with different pin counts simultaneously. The configuration can be changed to accommodate various product mixes based on pin count.
Inventors
- 👤 Marc R. Mydill
- 👤 Sam R. Pile
- 👤 Sheila O'Keefe
- 👤 Neal F. Okerblom
- 👤 W. Russ Keenan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/31907; G01R31/31917; G01R31/31922; G01R31/31926
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
73 words
A reconfigurable logic test system for testing integrated circuits, including at least two test modules, a test module comprising; a program controller; a first switching matrix; a pin group electronic circuit, connected to said program controller by said first switching matrix; a pin electronic circuit connected to the pin group electronic circuit; a second switching matrix; and at least one test head connectable to said pin electronic circuit by said second switching matrix.
Claim 2
Dependent Claim
73 words
A reconfigurable logic test system for testing integrated circuits, including at least two test modules, a test module comprising; a program controller; a first switching matrix; a pin group electronic circuit, connected to said program controller by said first switching matrix; a pin electronic circuit connected to the pin group electronic circuit; a second switching matrix; and at least one test head connectable to said pin electronic circuit by said second switching matrix.
Claim 3
Dependent Claim
37 words
The reconfigurable logic test system according to claim 1, including a synchronization circuit in said pin group electronic circuit to synchronize operation of said pin group electronic circuit and said pin electronic circuit with other test modules.
Claim 4
Dependent Claim
38 words
The reconfigurable logic test system according to claim 1, wherein two or more pin electronic circuits are combined to test integrated circuits having a higher pin count than a single pin electronic circuit has the capability of testing.
Claim 5
Dependent Claim
28 words
The reconfigurable logic test system according to claim I, wherein test heads having pin counts of 128, 256, 512 and 1024 are connected to the second switching matrix.
Claim 6
Dependent Claim
35 words
The reconfigurable logic test system according to claim 1, wherein each pin group circuit includes a time base circuit which is used for its own pins and for the pins of other pin electronics circuits.
Claim 7
Dependent Claim
30 words
The reconfigurable logic test system according to claim 5, including a multiplexing circuit which is used when running a plurality of pin group circuits from the same time base circuit.
Claim 8
Dependent Claim
39 words
The reconfigurable logic test system according to claim 5, wherein each time base circuit in each pin electronics circuit has programmable delays to compensate for skew when running a plurality of pin electronic circuits from the same time base.
Claim 9
Dependent Claim
38 words
The reconfigurable logic test system according to claim 1, wherein said pin group electronic circuit includes a central timing generator, a pattern sequence controller and functional and analog stimulus generation and response measurement circuitry for devices under test.
Claim 10
Dependent Claim
33 words
The reconfigurable logic test system according to claim 1, wherein the test system is configured to combine some test modules and not other test modules to conduct test on different type devices simultaneously.
Claim 11
Dependent Claim
23 words
The reconfigurable logic test system according to claim 1, wherein each test module can test a semiconductor device having up to 128 pins.
Claim 12
Dependent Claim
25 words
The reconfigurable logic test system according to claim 1, wherein two reconfigurable logic test modules can test a semiconductor device having up to 256 pins.
Claim 13
Dependent Claim
23 words
The reconfigurable logic test system according to claim 1, wherein test modules are combined to test semiconductor devices having pin multiples of 128.
Claim 14
Dependent Claim
27 words
The reconfigurable logic test system according to claim 1, including a configuration manager for reconfiguring the test system and each test module therein to a selected configuration.
Claim 15
Dependent Claim
25 words
The reconfigurable logic test system according to claim 13, wherein the each test module and the configuration manager are connected together on a common bus.
Claim 16
Dependent Claim
46 words
A reconfigurable logic test system comprising: a plurality of test modules; a configuration manager connected to said plurality of test modules along a common bus; wherein said configuration manager can configure the test modules to test one or more integrated circuits having different pin counts concurrently.
Claim 17
Dependent Claim
46 words
A reconfigurable logic test system comprising: a plurality of test modules; a configuration manager connected to said plurality of test modules along a common bus; wherein said configuration manager can configure the test modules to test one or more integrated circuits having different pin counts concurrently.
Claim 18
Dependent Claim
69 words
The reconfigurable logic test system according to claim 15, wherein said test modules each includes: a program controller; a first switching matrix; a pin group electronic circuit, connected to said program controller by said first switching matrix; a pin electronic circuit connected to the pin group electronic circuit; a second switching matrix; and at least one test head connectable to said pin electronic circuit by said second switching matrix.
Claim 19
Dependent Claim
37 words
The reconfigurable logic test system according to claim 16, including a synchronization circuit in said pin group electronic circuit to synchronize operation of said pin group electronic circuit and said pin electronic circuit with other test modules.
Claim 20
Dependent Claim
38 words
The reconfigurable logic test system according to claim 16, wherein two or more pin electronic circuits are combined to test integrated circuits having a higher pin count than a single pin electronic circuit has the capability of testing.
Claim 21
Dependent Claim
28 words
The reconfigurable logic test system according to claim 16, wherein test heads having pin counts of 128, 256, 512 and 1024 are connected to the second switching matrix.
Claim 22
Dependent Claim
34 words
The reconfigurable logic test system according to claim 16, wherein each pin group electronics circuit includes a time base circuit usable with its own pins and with the pins of other pin electronic circuits.
Claim 23
Dependent Claim
30 words
The reconfigurable logic test system according to claim 20, including a multiplexing circuit which is used when running a plurality of pin electronics circuit from the same time base circuit.
Claim 24
Dependent Claim
39 words
The reconfigurable logic test system according to claim 20, wherein each time base circuit in each pin electronics circuit has programmable delays to compensate for skew when running a plurality of pin electronic circuits from the same time base.
Claim 25
Dependent Claim
38 words
The reconfigurable logic test system according to claim 16, wherein said pin group electronic circuit includes a circuit timing generator, a pattern sequence controller and said pin electronic circuit includes analog test support functions for devices under test.
Claim 26
Dependent Claim
33 words
The reconfigurable logic test system according to claim 16, wherein the test system is configured to combine some test modules and not other test modules to conduct test on different type devices simultaneously.
Claim 27
Dependent Claim
23 words
The reconfigurable logic test system according to claim 16, wherein each test module can test a semiconductor device having up to 128 pins.
Claim 28
Dependent Claim
25 words
The reconfigurable logic test system according to claim 16, wherein two reconfigurable logic test modules can test a semiconductor device having up to 256 pins.
Claim 29
Dependent Claim
23 words
The reconfigurable logic test system according to claim 16, wherein test modules are combined to test semiconductor devices having pin multiples of 128.
Claim 30
Independent Claim
88 words
A method of reconfiguring a logic test system to test integrated circuits having a pin count from 128 pins to at least 1024 pins, the test system including a plurality of test modules each having a controller and each having electronic testing and measuring circuits to test 128 pins, comprising the steps of; combining two or more test modules to provide test resources to test the desired number of pins, synchronizing the test modules, and programming the combined modules with a single controller from one of the modules.
Claim 31
Independent Claim
88 words
A method of reconfiguring a logic test system to test integrated circuits having a pin count from 128 pins to at least 1024 pins, the test system including a plurality of test modules each having a controller and each having electronic testing and measuring circuits to test 128 pins, comprising the steps of; combining two or more test modules to provide test resources to test the desired number of pins, synchronizing the test modules, and programming the combined modules with a single controller from one of the modules.
Claim 32
Dependent Claim
45 words
The method according to claim 28, including the step of separating test modules to test a plurality of integrated circuits having a smaller pin count, and also combining test modules to test an integrated circuit of a higher pin count than said smaller pin count.
Claim 33
Dependent Claim
52 words
The method according to claim 28 wherein a timing reference is used in synchronizing the test modules, including the step of using the timing reference from one test module of the combined test modules and providing a variable delay so that each test module receives the timing reference at the same time.
Claim 34
Dependent Claim
32 words
The method according to claim 28, including the step of multiplexing the combined electronic resources to test an integrated circuit requiring greater electronic resources support than possible with a single test module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-17 | 1994-12-17 | 1995-06-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-17 | 1998-12-17 | 1999-06-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-17 | 2002-12-17 | 2003-06-18 | $7700.00 | Window Closed / Lapsed |