Pipelined Fast Fourier Transform (FFT) architecture

Claim 2

A radix-R FFT (Fast Fourier Transform) architecture comprising: a memory for storing complex number data, said memory comprising no more than a selected number N memory locations during operation, wherein N is the size of the FFT an there is a positive integer R and N is a power of R; a pipelined data path comprising circuitry to perform computation operations and including an output stage, said pipelined data path coupled to said memory for accessing R complex number data therefrom, for computing an FFT butterfly, and storing R results from said output stage of said pipelined data path to said memory during one pipeline cycle.

Claim 3

The architecture, as set forth in claim 1, further comprising address circuitry coupled to said memory for generating memory read and write addresses.

Claim 4

The architecture, as set forth in claim 1, wherein said pipelined data path comprises: a plurality of adders for summing said complex number data from said memory and producing a plurality of summed data, each said adders having an output; a first plurality of pipeline buffers, each said pipeline buffer having an input and an output each said pipeline buffer inputs coupled to a corresponding adder output; and a plurality of multipliers coupled to said plurality of adders for receiving said plurality of summed data multiplying said summed data and a set of predetermined twiddle coefficients, and producing a plurality of complex number products, each said multiplier having an input coupled to a corresponding pipeline buffer output.

Claim 5

The architecture, as set forth in claim 3, further comprising: a coefficient memory coupled to said plurality of multipliers for storing said set of twiddle coefficients; and coefficient address circuitry coupled to said coefficient memory for generating coefficient memory read addresses.

Claim 6

The architecture, as set forth in claim 3, further comprising: detection circuitry coupled to said plurality of multipliers for receiving said plurality of complex products and producing a scaling factor; and scaling circuitry coupled to said detection circuitry and said memory for scaling said data accessed herefrom in response to said scaling factor.

Claim 7

The architecture, as set forth in claim 1, further comprising permutation circuitry coupled to said memory, said memory storing said complex number data in a predetermined sequence, said permutation circuitry for altering said predetermined sequence of said complex number data prior to entering said pipelined data path.

Claim 8

The architecture, as set forth in claim 1, wherein said memory includes R banks of random access memory, each bank of memory for storing N/R complex number data, with one complex number data being accessed from each of said R banks concurrently.

Claim 9

The architecture, as set forth in claim 1, wherein said memory includes four banks of random access memory, each bank for storing N/4 complex number data, with one complex number data being accessed from each of said four banks concurrently during the first half of said pipelined cycle, wherein N is a power of 4.

Claim 10

The architecture, as set forth in claim 8, wherein said pipelined data path comprises: sixteen adders for summing four complex number data from said memory and producing four complex number sums during said pipeline cycle; three complex multipliers coupled to said adders for receiving three of said four complex number sums, multiplying said three sums and three twiddle coefficients, and producing three complex number products during said pipeline cycle; and a plurality of pipeline buffers coupled between said sixteen adders and said three complex multipliers.

Claim 11

An N-point radix-R, where R is a positive integer and N is a power of R, decimation-in-frequency Fast Fourier Transform (FFT) architecture comprising: a memory for storing data, said memory comprising no more than a selected number N memory locations during operations, wherein N is the size of the FFT; a plurality of adders coupled to said memory for summing R data and producing a plurality of sums; a plurality of pipelined complex multipliers coupled to said plurality of adders for receiving said plurality of sums, multiplying said plurality of sums with a set of predetermined twiddle coefficients, and producing a plurality of products; and a plurality of pipelines buffers coupled between said plurality of adders and said plurality of complex multipliers and a final stage buffer, said final stage buffer for storing a plurality of results into si memory during one pipeline cycle.

Claim 12

An N-point radix-R, where R is a positive integer and N is a power of R, decimation-in-frequency Fast Fourier Transform (FFT) architecture comprising: a memory for storing data, said memory comprising no more than a selected number N memory locations during operations, wherein N is the size of the FFT; a plurality of adders coupled to said memory for summing R data and producing a plurality of sums; a plurality of pipelined complex multipliers coupled to said plurality of adders for receiving said plurality of sums, multiplying said plurality of sums with a set of predetermined twiddle coefficients, and producing a plurality of products; and a plurality of pipelines buffers coupled between said plurality of adders and said plurality of complex multipliers and a final stage buffer, said final stage buffer for storing a plurality of results into si memory during one pipeline cycle.

Claim 13

The architecture, as set forth in claim 10, further comprising address circuitry coupled to said memory for generating memory read and write addresses.

Claim 14

The architecture, as set forth in claim 10, further comprising: a coefficient memory coupled to said plurality of multipliers for storing said set of twiddle coefficients; and coefficient address circuitry coupled to said coefficient memory for generating coefficient memory read addresses.

Claim 15

The architecture, as set forth in claim 10, further comprising: detection circuitry coupled to said plurality of complex multipliers for receiving said plurality of products and producing a scaling factor; and scaling circuitry coupled to said detection circuitry and said memory for scaling said data accessed therefrom in response to said scaling factor.

Claim 16

The architecture, as set forth in claim 10, further comprising permutation circuitry coupled to said memory, said memory storing said data in a predetermined sequence, said permutation circuitry for altering said predetermined sequence of said data prior to entering said plurality of multipliers.

Claim 17

The architecture, as set forth in claim 10, wherein said memory includes R banks of random access memory, each bank of memory for storing N/R complex number data, with one complex number data being accessed from each of said R banks concurrently.

Claim 18

The architecture, as set forth in claim 10, wherein said memory includes four banks of random access memory, each bank for storing N/4 complex number data, with one complex number data being accessed from each of said four banks concurrently during the first half of said pipeline cycle.

Claim 19

The architecture, as set forth in claim 16, wherein sixteen adders sum four complex number data from said memory and produce four complex number sums during said pipeline cycle; and three complex multipliers multiply said sums and three twiddle coefficients, and produce three complex number products during said pipeline cycle.

Claim 20

The architecture, as set forth in claim 10, further comprising permutation circuitry coupled to said plurality of multipliers for receiving said plurality of products and altering the sequence of said products, said permutation circuitry coupled to said memory and storing said products in the altered sequence therein.

Claim 21

An N-point, radix-R, where R is a positive integer an N is a power of R, decimation-in-frequency Fast Fourier Transform (FFT) computing circuit comprising: R banks of memory for storing no more than N data during operation, each of said R banks storing N/R data and arranged for accessing R data therefrom concurrently; a first permutation network coupled to said R banks of memory for receiving said R data; scaling circuit coupled to said permutation network for scaling said R data in response to a predetermined scaling factor; a plurality of adders coupled to said scaling circuit for summing said R data and producing R sums; a coefficient memory for storing a set of twiddle coefficients; a plurality of multiplier coupled to said adders and said coefficient memory for performing multiplications of said R sums and said set of twiddle coefficients and producing R products; detection circuitry coupled to said plurality of multipliers for receiving said R products and producing said scaling factor; and a second permutation network coupled to said detection circuitry for inputting said R products and reordering the sequence of said R products, said second permutation network coupled to said R banks of memory and storing said R products therein.

Claim 22

An N-point, radix-R, where R is a positive integer an N is a power of R, decimation-in-frequency Fast Fourier Transform (FFT) computing circuit comprising: R banks of memory for storing no more than N data during operation, each of said R banks storing N/R data and arranged for accessing R data therefrom concurrently; a first permutation network coupled to said R banks of memory for receiving said R data; scaling circuit coupled to said permutation network for scaling said R data in response to a predetermined scaling factor; a plurality of adders coupled to said scaling circuit for summing said R data and producing R sums; a coefficient memory for storing a set of twiddle coefficients; a plurality of multiplier coupled to said adders and said coefficient memory for performing multiplications of said R sums and said set of twiddle coefficients and producing R products; detection circuitry coupled to said plurality of multipliers for receiving said R products and producing said scaling factor; and a second permutation network coupled to said detection circuitry for inputting said R products and reordering the sequence of said R products, said second permutation network coupled to said R banks of memory and storing said R products therein.

Claim 23

An N-point, where N is a power of 4, radix-4, decimation-in-frequency FFT (Fast Fourier Transform) computing circuit comprising: four banks of memory for storing no more than N data during operation, each of said four banks storing N/4 data and arranged for accessing four data therefrom concurrently; a first permutation network coupled to said four banks of memory for receiving said four data; scaling circuitry coupled to said permutation network for scaling said four data in response to a predetermined scaling factor; a plurality of adders coupled to said scaling circuit for summing said four data and producing four sums; a coefficient memory for storing a set of twiddle coefficients; a plurality of multipliers coupled to said adders and to said coefficient memory for performing multiplications of said four sums and said set of twiddle coefficients an producing four products; detection circuitry coupled to said plurality of multipliers of receiving said four products and producing said scaling factor; and a second permutation network coupled to said detection circuit for receiving said four products and reordering the sequence of said four products, said second permutation network coupled to said four banks of memory and storing said four products therein.

Claim 24

An N-point, where N is a power of 4, radix-4, decimation-in-frequency FFT (Fast Fourier Transform) computing circuit comprising: four banks of memory for storing no more than N data during operation, each of said four banks storing N/4 data and arranged for accessing four data therefrom concurrently; a first permutation network coupled to said four banks of memory for receiving said four data; scaling circuitry coupled to said permutation network for scaling said four data in response to a predetermined scaling factor; a plurality of adders coupled to said scaling circuit for summing said four data and producing four sums; a coefficient memory for storing a set of twiddle coefficients; a plurality of multipliers coupled to said adders and to said coefficient memory for performing multiplications of said four sums and said set of twiddle coefficients an producing four products; detection circuitry coupled to said plurality of multipliers of receiving said four products and producing said scaling factor; and a second permutation network coupled to said detection circuit for receiving said four products and reordering the sequence of said four products, said second permutation network coupled to said four banks of memory and storing said four products therein.