US5162801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low noise switched capacitor digital-to-analog converter
Assignee: Raytheon Co
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Filing: 1991-12-02
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Granted: 1992-11-10
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Expires: 2011-12-02
Abstract
Abstract A low-noise switched-capacitor DAC converts an integer number from an N-bit digital format into an analog voltage level by transferring charge between two appropriately ratioed capacitors using a plurality of switches. The switches select only an appropriate one of a plurality of capacitors to connect to an operational amplifier in accordance with any digital input. The sampled kT/C noise and switch charge injection from an N-bit DAC is thus beneficially reduced.
Inventors
- 👤 Scott R. Powell
- 👤 Anthony G. Mellissinos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:49
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/74; H03M1/76; H03M1/765
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
147 words
Apparatus for digital-to-analog signal conversion comprising an operational amplifier having an output terminal and an input terminal, a reference capacitor connected between the output terminal and the input terminal, a plurality of capacitors switchably connected to the input terminal of the operational amplifier, each of said capacitors having a different capacitance value, means for selectively switchably connecting each of said plurality of capacitors to a voltage source for developing a voltage across said capacitors and said reference capacitor, and said switch means being operative for causing a selection of only an appropriate one of said capacitors in correspondence with any received digital signal to develop the voltage and the others to remain in a floating voltage state whereby thermal noise and charge injection of said others of the capacitors do not contribute such noise to the output signal level at the output terminal of the operational amplifier.
Claim 2
Dependent Claim
147 words
Apparatus for digital-to-analog signal conversion comprising an operational amplifier having an output terminal and an input terminal, a reference capacitor connected between the output terminal and the input terminal, a plurality of capacitors switchably connected to the input terminal of the operational amplifier, each of said capacitors having a different capacitance value, means for selectively switchably connecting each of said plurality of capacitors to a voltage source for developing a voltage across said capacitors and said reference capacitor, and said switch means being operative for causing a selection of only an appropriate one of said capacitors in correspondence with any received digital signal to develop the voltage and the others to remain in a floating voltage state whereby thermal noise and charge injection of said others of the capacitors do not contribute such noise to the output signal level at the output terminal of the operational amplifier.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1 wherein said switch means further comprises means for simultaneously discharging the plurality of capacitors.
Claim 4
Dependent Claim
21 words
The apparatus of claim 1 wherein the respective capacitances of the plurality of capacitors are decreasing fractions of a selected capacitance.
Claim 5
Dependent Claim
22 words
The apparatus of claim 1 wherein said switch means includes means for selectively applying another voltage source to the plurality of capacitors.
Claim 6
Dependent Claim
35 words
The apparatus of claim 1 wherein the switch means comprises a decoder wherein the digital signal is decoded to provide a switch selection signal to select one of the capacitors from said plurality of capacitors.
Claim 7
Dependent Claim
34 words
The apparatus of claim 5 wherein the switch means includes means for selectively applying another voltage source to the plurality of capacitors and the selection signal further selects the voltage source to be applied.
Claim 8
Dependent Claim
104 words
A DAC circuit comprising an operational amplifier having an output terminal, an inverting input terminal and a non-inverting input terminal; a reference capacitor connected between the output terminal and the inverting terminal; a plurality of capacitors switchably connected to the inverting terminal of the operational amplifier; means for switchably connecting each one of said plurality of capacitors to one of two voltage sources for developing a voltage across said one of said capacitors and said reference capacitor, and switch means operative for causing a selection of only an appropriate one of said capacitors in correspondence to any received digital signal to develop the voltage.
Claim 9
Dependent Claim
104 words
A DAC circuit comprising an operational amplifier having an output terminal, an inverting input terminal and a non-inverting input terminal; a reference capacitor connected between the output terminal and the inverting terminal; a plurality of capacitors switchably connected to the inverting terminal of the operational amplifier; means for switchably connecting each one of said plurality of capacitors to one of two voltage sources for developing a voltage across said one of said capacitors and said reference capacitor, and switch means operative for causing a selection of only an appropriate one of said capacitors in correspondence to any received digital signal to develop the voltage.
Claim 10
Dependent Claim
19 words
The apparatus of claim 7 wherein said switch means further comprises means for simultaneously discharging the plurality of capacitors.
Claim 11
Dependent Claim
21 words
The apparatus of claim 7 wherein the respective capacitances of the plurality of capacitors are decreasing fractions of a selected capacitance.
Claim 12
Dependent Claim
35 words
The apparatus of claim 7 wherein the switch means comprises a decoder wherein the digital signal is decoded to provide a switch selection signal to select one of the capacitors from said plurality of capacitors.
Claim 13
Independent Claim
132 words
A method for converting a digital value to an analog signal level comprising the steps of providing an operational amplifier having an input terminal and an output terminal, connecting a reference capacitor between the input and output terminals, connecting a plurality of capacitors to the input terminal, selecting only an appropriate one of said plurality of capacitors in correspondence with any determined digital input value and applying a voltage thereto to establish a selected voltage output at the output terminal of the operational amplifier while allowing each of the others of said plurality of capacitors to remain in a floating voltage state. whereby thermal noise and charge injection of said others of the capacitors will not contribute such noise to the output signal level at the output terminal of the operational amplifier.
Claim 14
Independent Claim
132 words
A method for converting a digital value to an analog signal level comprising the steps of providing an operational amplifier having an input terminal and an output terminal, connecting a reference capacitor between the input and output terminals, connecting a plurality of capacitors to the input terminal, selecting only an appropriate one of said plurality of capacitors in correspondence with any determined digital input value and applying a voltage thereto to establish a selected voltage output at the output terminal of the operational amplifier while allowing each of the others of said plurality of capacitors to remain in a floating voltage state. whereby thermal noise and charge injection of said others of the capacitors will not contribute such noise to the output signal level at the output terminal of the operational amplifier.
Claim 15
Dependent Claim
37 words
The method of claim 11 wherein the step of selecting one of the plurality of capacitors further comprises the step of decoding the input digital value and providing a selection signal in accordance with the digital signal.
Claim 16
Dependent Claim
31 words
The method of claim 11 further comprising the step of discharging each of the plurality of capacitors prior to the step of applying voltage to the selected one of the capacitors.
References Cited (Backward Citations)
US4077035A
Cited
US4667179A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-10 | 1996-05-11 | 1996-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-10 | 2000-05-11 | 2000-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-10 | 2004-05-11 | 2004-11-10 | $7700.00 | Window Closed / Lapsed |