Sample-and-hold circuit device

Claim 2

A sample-and-hole circuit device comprising: input signal terminal means for receiving an input signal; output terminal means; reference potential terminal means having a reference potential; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal means, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element and said output terminal means and said reference potential terminal means; and a switch means which is turned on or off by a second control signal so as to selectively connect said output terminal means to said reference potential terminal means.

Claim 3

A device according to claim 1, further comprising a third switch means which is turned on by the second control signal, for connecting said output of said MOS transistor and the first terminal of said non-linear element to said potential terminal means.

Claim 4

A device according to claim 1, further comprising second potential holding means connected between said output of said MOS transistor and the first terminal of said non-linear element and said reference potential terminal means.

Claim 5

A device according to claim 1, further comprising third switch means, turned on by a third control signal, for connecting said output of said MOS transistor and the first terminal of said non-linear element to said reference potential terminal means.

Claim 6

A sample-and-hold circuit device comprising: input terminal means for receiving an input signal; output terminal means; reference potential terminal having a reference potential; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal means, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element and said output terminal means and said reference potential terminal; and current source means which is controlled in response to a second control signal so as to connect said output terminal means to said reference potential terminal.

Claim 7

A sample-and-hold circuit device comprising: input terminal means for receiving an input signal; output terminal means; reference potential terminal having a reference potential; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal means, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element and said output terminal means and said reference potential terminal; and current source means which is controlled in response to a second control signal so as to connect said output terminal means to said reference potential terminal.

Claim 8

A sample-and-hold circuit device comprising: first sample-and-hold means for sampling and holding an input signal; and second sample-and-hold means, having a high input impedance, for sampling and holding an output from said first sample-and-hold means, wherein said first sample-and-hold means comprises: an input signal terminal for receiving the input signal; an output terminal; a reference potential terminal having a reference potential; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element an said output terminal and said reference potential terminal; and a switch means which is turned on by a second control signal to connect said output terminal to said reference potential terminal.

Claim 9

A sample-and-hold circuit device comprising: first sample-and-hold means for sampling and holding an input signal; and second sample-and-hold means, having a high input impedance, for sampling and holding an output from said first sample-and-hold means, wherein said first sample-and-hold means comprises: an input signal terminal for receiving the input signal; an output terminal; a reference potential terminal having a reference potential; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element an said output terminal and said reference potential terminal; and a switch means which is turned on by a second control signal to connect said output terminal to said reference potential terminal.

Claim 10

A sample-and-hold circuit device comprising: first sample-and-hold means for sampling and holding an input signal; and second sample-and-hold means, having a high input impedance, for sampling and holding an output from said first sample-and-hold means, wherein said second sample-and-hold means comprises: first buffer means for receiving, as an input signal, said output from said first sample-and-hold means; a sample-and-hold circuit for sampling and holding an output from said first buffer means; and a voltage follower, having second buffer means and level shift means arranged in a negative feedback path of said voltage follower, wherein said sample-and-hold circuit of said second sample-and-hold means comprises: an input signal terminal for receiving the input signal; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element and said output terminal and said reference potential terminal; and a switch means which is turned on by a second control signal to connect said output terminal to said reference potential terminal.

Claim 11

A sample-and-hold circuit device comprising: first sample-and-hold means for sampling and holding an input signal; and second sample-and-hold means, having a high input impedance, for sampling and holding an output from said first sample-and-hold means, wherein said second sample-and-hold means comprises: first buffer means for receiving, as an input signal, said output from said first sample-and-hold means; a sample-and-hold circuit for sampling and holding an output from said first buffer means; and a voltage follower, having second buffer means and level shift means arranged in a negative feedback path of said voltage follower, wherein said sample-and-hold circuit of said second sample-and-hold means comprises: an input signal terminal for receiving the input signal; a MOS transistor having an input connected to said input signal terminal means, an output, and a gate terminal supplied with a first control signal, said MOS transistor producing an error charge when it is turned off by the first control signal; a non-linear element having a first terminal connected to the output of said MOS transistor, and a second terminal connected to said output terminal, said non-linear element being turned off by the error charge; potential holding means connected between the second terminal of said non-linear element and said output terminal and said reference potential terminal; and a switch means which is turned on by a second control signal to connect said output terminal to said reference potential terminal.