EP0114475A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improvements in or relating to sample-and-hold circuits
Assignee: AT&T Inc
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Filing: 1983-12-12
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Granted: —
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Expires: 2003-12-12
Abstract
Abstract A feedback sample-and-hold circuit (16) includes a primary (30,32) branch and a secondary (34,36) sample-and-hold branch for correction of offset voltage in the primary branch which results from switching charge feedthrough of its sampling switch. A pair of N-channel buffer transistors (44, 46) one an enhancement type and one a depletion type, are so connected to the branches that power supply noise is attenuated. Additionally, the parasitic capacitance of the enhancement transistor acts as a coupling capacitor for the correction function.
Inventors
- 👤 Eric John Swanson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:55
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
165 words
A sample-and-hold circuit including a sampling switch (30) connected between a signal input and an input of a buffer (42), a holding capacitor (32) connected at a first side to the input of the buffer and at a second side to a reference potential, and a feedback means (52,54,24) connected to the output of the buffer and to an input of an amplifier, and CHARACTERISED IN THAT there is provided a correction switch (34) connected at its first side to the output of the amplifier, and a correction holding capacitor (36) connected at its first side to a reference potential and at its second side to the second side of the correction switch, and the buffer includes an enhancement mode transistor (46) having a gate serving as the said input of the buffer and its drain-to-source conduction path connected to bias current means (47), and means (44) coupling the second side of the correction switch (34) to the drain of the enhancement mode transistor (46).
Claim 2
Dependent Claim
165 words
A sample-and-hold circuit including a sampling switch (30) connected between a signal input and an input of a buffer (42), a holding capacitor (32) connected at a first side to the input of the buffer and at a second side to a reference potential, and a feedback means (52,54,24) connected to the output of the buffer and to an input of an amplifier, and CHARACTERISED IN THAT there is provided a correction switch (34) connected at its first side to the output of the amplifier, and a correction holding capacitor (36) connected at its first side to a reference potential and at its second side to the second side of the correction switch, and the buffer includes an enhancement mode transistor (46) having a gate serving as the said input of the buffer and its drain-to-source conduction path connected to bias current means (47), and means (44) coupling the second side of the correction switch (34) to the drain of the enhancement mode transistor (46).
Claim 3
Dependent Claim
41 words
A circuit as claimed in claim 1 wherein the coupling means (44) includes a depletion mode transistor having its gate connected to the second side of the correction switch (34) and its drain-to-source conduction path connected to bias current means (47).
Claim 4
Dependent Claim
74 words
A circuit as claimed in claim 2 wherein the transistors have the same conduction channel polarity, the depletion mode transistor has its source connected to the drain of the enhancement mode transistor and its drain connected to supply voltage means (V DD ) of a first polarity, and the source of the enhancement transistor is connected in series with the bias current means to supply voltage means (V SS ) of the opposite polarity.
Claim 5
Dependent Claim
27 words
A circuit as claimed in any preceding claim including means (13) for sampling and holding a signal prior to its application to an input of the amplifier.
References Cited (Backward Citations)
No citation records indexed.
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