Phonon suppression in quantum wells

Claim 2

An enhanced mobility semiconductor comprising: a quantum well comprising at least two charge carrier barrier layers of a wide bandgap material, each of the two charge carrier barrier layers being separated by a conductive layer containing charge carriers, wherein each conducting layer is at least ten monolayers thick; and a number of phonon barriers having a predetermined thickness formed in the conducting layer, wherein the predetermined thickness is chosen to allow charge carrier tunneling through the phonon barriers and the phonon barriers comprise a material having a substantially different elastic constant than the conducting layer, wherein the phonon barriers are separated from each other by a predetermined spacing chosen to minimize charge carrier interaction with phonons in the conducting layer and with interface phonons generated at an interface between the phonon barriers and the conducting layer.

Claim 3

The semiconductor of claim 1 further comprising planar doping layers formed in the charge carrier barrier layers.

Claim 4

The semiconductor of claim 2 further comprising a transfer well formed in the conducting layer between an outermost phonon barrier and one of the charge carrier barrier layers.

Claim 5

The semiconductor of claim 1 wherein the phonon barriers comprise aluminum arsenide, the conducting layer comprises gallium arsenide, the at least two charge carrier barrier layers comprise aluminum arsenide, and the predetermined spacing is in the range of ten to thirty monomolecular layers of gallium arsenide.

Claim 6

An enhanced mobility semiconductor comprising: a crystal substrate having a surface; a plurality of superimposed layers of semiconductor material disposed on the substrate essentially parallel to the surface, at least two of the layers being conducting layers containing charge carriers, each of the at least two conducting layers being separated by a phonon barrier which prohibits phonons of a first of the at least two conducting layers from penetrating into a second of the at least two conducting layers, wherein the phonon barrier comprises a material with a different elastic constant than the at least two conducting layers and the at least two conducting layers have a predetermined thickness greater than ten monolayers, wherein the predetermined thickness is chosen to minimize interaction between the charge carriers and interface phonons at an interface between the conducting layers and the phonon barriers.

Claim 7

An enhanced mobility semiconductor comprising: a crystal substrate having a surface; a plurality of superimposed layers of semiconductor material disposed on the substrate essentially parallel to the surface, at least two of the layers being conducting layers containing charge carriers, each of the at least two conducting layers being separated by a phonon barrier which prohibits phonons of a first of the at least two conducting layers from penetrating into a second of the at least two conducting layers, wherein the phonon barrier comprises a material with a different elastic constant than the at least two conducting layers and the at least two conducting layers have a predetermined thickness greater than ten monolayers, wherein the predetermined thickness is chosen to minimize interaction between the charge carriers and interface phonons at an interface between the conducting layers and the phonon barriers.

Claim 8

The semiconductor of claim 5 wherein the phonon barrier allows the charge carriers to tunnel from the first conducting layer to the second conducting layer.

Claim 9

The semiconductor of claim 5 wherein the at least two conducting layers comprise gallium arsenide and the phonon barrier comprises aluminum arsenide.

Claim 10

The semiconductor of claim 5 wherein the phonon barrier confines the phonons of the at least two conducting layers in at least one dimension.

Claim 11

The semiconductor of claim 7 wherein the predetermined thickness is in the range of ten to thirty monomolecular layers of gallium arsenide.

Claim 12

An enhanced mobility semiconductor comprising: first and second phonon barriers comprising a wide bandgap material; at least two phonon wells of a predetermined minimum thickness greater than ten monolayers formed between the first and second phonon barriers, each of the at least two phonon wells being separated by a third phonon barrier, wherein the phonon wells comprise a material with a different elastic constant than the phonon barriers, thereby confining phonons within the at least two phonon wells, wherein the third phonon barrier is sufficiently thin to allow significant charge carrier tunneling through the third phonon barrier and the predetermined minimum thickness is chosen to minimize charge carrier interaction with interface phonons.

Claim 13

An enhanced mobility semiconductor comprising: first and second phonon barriers comprising a wide bandgap material; at least two phonon wells of a predetermined minimum thickness greater than ten monolayers formed between the first and second phonon barriers, each of the at least two phonon wells being separated by a third phonon barrier, wherein the phonon wells comprise a material with a different elastic constant than the phonon barriers, thereby confining phonons within the at least two phonon wells, wherein the third phonon barrier is sufficiently thin to allow significant charge carrier tunneling through the third phonon barrier and the predetermined minimum thickness is chosen to minimize charge carrier interaction with interface phonons.

Claim 14

The semiconductor of claim 1 wherein the phonon wells are conductive layers containing charge carriers.

Claim 15

The semiconductor of claim 10 wherein the phonon wells comprise gallium arsenide, the phonon barriers comprise aluminium arsenide, and the predetermined thickness is in the range of ten to thirty monomolecular layers.