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US5160900A
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Method to speed up the training of a shift oscillator in a frequency synthesizer
Assignee: Nokia Oyj
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Filing: 1992-01-21
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Granted: 1992-11-03
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Expires: 2012-01-21
Abstract
Abstract A method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit. The circuit comprises a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7). When the training process is started, the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.
Inventors
- 👤 Pauli Visuri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1972
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
119 words
Method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit comprising a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7), characterized in that when the training process is started the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.
Claim 2
Dependent Claim
119 words
Method to speed up the training of the output frequency signal (Out) of a frequency synthesizer circuit comprising a voltage controlled oscillator (7) controlled by a filtered (6) feedback signal (Fb) output by a phase detector circuit (5) having a first input signal (Rs), which is produced by a reference counter (3) dividing an external reference signal produced by a reference oscillator (2), and a second input signal (Cs) produced by a programmable counter (4) dividing an output signal (Vs) from the voltage controlled oscillator (7), characterized in that when the training process is started the internal reference frequency of the first and second input signals (Rs, Cs) is simultaneously increased by a predetermined amount for a predetermined time.
Claim 3
Dependent Claim
24 words
Method according to claim 1, characterized in that said frequency increase is controlled by reducing the factors (1/R, 1/N) of the counters (3, 4).
Claim 4
Dependent Claim
34 words
Method according to claim 2, characterized in that the change of the factors is controlled by a synchronous programming circuit (1) producing as outputs data control signals (Dr, Dc) to said counters (3, 4).
Claim 5
Dependent Claim
41 words
Method according to claim 3, characterized in that the exact moment of said frequency increase is determined by a control signal (Ps) produced by the phase detector circuit (5) enabling the change of the outputs of the synchronous programming circuit (1).
Claim 6
Dependent Claim
26 words
Method according to claim 4, characterized in that said exact moment is selected as the moment when the phase of the phase detector (5) is zero.
Claim 7
Dependent Claim
129 words
A control circuit for increasing the speed of training of a radiotelephone shift oscillator, the combination comprising: a reference counter; a programmable counter; phase detector means connected to said reference and programmable counters to provide a signal indicative of a phase difference between signals generated by said counters; variable shift oscillator means responsive to an output from said phase detector means for producing an output frequency signal and for producing a feedback signal to said programmable counter to control the operation of said programmable counter; and programming means for controlling the frequency of operation of said reference and programmable counters, said programming means including means for increasing the frequency of operation of both said reference and programmable counter upon the commencement of training of said variable shift oscillator means.
Claim 8
Dependent Claim
129 words
A control circuit for increasing the speed of training of a radiotelephone shift oscillator, the combination comprising: a reference counter; a programmable counter; phase detector means connected to said reference and programmable counters to provide a signal indicative of a phase difference between signals generated by said counters; variable shift oscillator means responsive to an output from said phase detector means for producing an output frequency signal and for producing a feedback signal to said programmable counter to control the operation of said programmable counter; and programming means for controlling the frequency of operation of said reference and programmable counters, said programming means including means for increasing the frequency of operation of both said reference and programmable counter upon the commencement of training of said variable shift oscillator means.
Claim 9
Dependent Claim
47 words
The control circuit as recited in claim 6 wherein each said reference counter and programmable counter includes division means for controlling the output frequency of each said counter, said programming means controlling said division means to accomplish said increased frequency operation of said reference and programmable counters.
Claim 10
Dependent Claim
44 words
The control circuit as recited in claim 7 wherein said phase detector means produces a control signal that is fed to said programming means to cause said programming means to enable said increase in the frequency of operation of said reference and programmable counters.
Claim 11
Dependent Claim
32 words
The control circuit as recited in claim 8 wherein said control signal from said phase detector means is generated when the inputs to said phase detector means indicate a zero phase difference.
Claim 12
Dependent Claim
47 words
A control circuit as recited in claim 6 further comprising a microprocessor for controlling the operation of said radiotelephone, said microprocessor providing input signals to said programming means to cause the generation of signals that affect a change in output frequencies from said reference and programmable counters.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |