Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws

Claim 2

Digital electronic computer in which memory is addressed from a memory array by using address sequences to identify specific groups of one or more bits, the digital electronic computer comprising: a) a memory array addressed by using an address of a first type to select a memory page, and an address of a second type to select specific bits or groups of bits within a specified page, wherein the memory array can remain within a single page for several successive memory accesses with less time required to access specific bits within said single page on all accesses after an initial page access (called page mode access); b) a memory address circuit for addressing the memory array in accordance with address sequences, the address sequences including memory addresses of the first type, the first type of address sequence being a row address sequence, and address sequences of a second type, in the form of page mode memory addresses; c) a logic circuit connected to the memory address circuit and the memory array and operating to control addressing of the memory in accordance with the address sequences, the logic circuit being responsive to bus signals so as to permit selection of a number of sequential matches of the first type of addresses or the number of sequential mismatches of the first type of addresses needed to switch between using and not using page mode accesses; d) an address comparator for comparing sequential addresses of a first type for sequential matches; and e) a means of modifying operation of said logic circuit by selectively maintaining addresses of the first type at a state which reduces access time for sequential addresses exhibiting the sequential matches of the first type.

Claim 3

Computer as described in claim 1, further comprising: the operation of the logic circuit being modified in accordance with a relative number of sequential matches of the address sequences and a number of sequential mismatches of the address sequences so that page mode access is utilized when the relative number of matches is higher than a predetermined number of matches, and page mode access is not used when the relative number of matches is lower than a predetermined number of matches.

Claim 4

Computer as described in claim 2, further comprising: a) the memory address circuit including a refresh circuit for refreshing the address sequences b) refresh address used for RAS only refresh cycles, thereby permitting the logic circuit to monitor the address sequences that will be refreshed and cancel refreshing the address sequences if current address sequences are the same.

Claim 5

Television display system in which memory is addressed from a memory array by using address sequences in specified patterns, comprising: a) a memory array addressed by using an address of a first type to select a memory page, and an address of a second type to select specific bits or groups of bits within a specified page, wherein the memory array can remain within a single page for several successive memory accesses with less time required to access specific bits within said single page on all accesses after an initial page access; b) a memory address circuit for addressing the memory array in accordance with address sequences, the address sequences including memory addresses of the first type, the first type of address sequence being row address sequence, and memory addresses of the second type; c) a logic circuit connected to the memory address circuit and the memory array and operating to control addressing of the memory in accordance with the address sequences, the operation of the logic circuit being modified in accordance with a relative number of sequential matches of the address sequences; d) an address comparator for comparing sequential addresses of a first type for sequential matches; and e) a means of modifying operation of said logic circuit by selectively maintaining addresses of the first type at a state which reduces access time for sequential addresses of the first type, wherein the logic circuit is responsive to bus signals so as to permit selection of the number of sequential matches of the first type of addresses or a number of sequential mismatches of the first type of addresses needed to switch between using and not using page mode accesses.

Claim 6

Television display system in which memory is addressed from a memory array by using address sequences in specified patterns, comprising: a) a memory array addressed by using an address of a first type to select a memory page, and an address of a second type to select specific bits or groups of bits within a specified page, wherein the memory array can remain within a single page for several successive memory accesses with less time required to access specific bits within said single page on all accesses after an initial page access; b) a memory address circuit for addressing the memory array in accordance with address sequences, the address sequences including memory addresses of the first type, the first type of address sequence being row address sequence, and memory addresses of the second type; c) a logic circuit connected to the memory address circuit and the memory array and operating to control addressing of the memory in accordance with the address sequences, the operation of the logic circuit being modified in accordance with a relative number of sequential matches of the address sequences; d) an address comparator for comparing sequential addresses of a first type for sequential matches; and e) a means of modifying operation of said logic circuit by selectively maintaining addresses of the first type at a state which reduces access time for sequential addresses of the first type, wherein the logic circuit is responsive to bus signals so as to permit selection of the number of sequential matches of the first type of addresses or a number of sequential mismatches of the first type of addresses needed to switch between using and not using page mode accesses.

Claim 7

Television display system as described in claim 4, further comprising: a) the memory address circuit including a refresh circuit for refreshing the address sequences b) refresh address used for RAS only refresh cycles, thereby permitting the logic circuit to monitor the address sequences that will be refreshed and cancel refreshing the address sequences if current address sequences are the same.

Claim 8

Television display system in which memory is addressed from a memory array by using address sequences in specified patterns, the television display system comprising: a) a memory array addressed by using an address of a first type to select a memory page, and an address of a second type to select specific bits or groups of bits within a specified page, wherein the memory array which can remain within a single page for several successive memory accesses with less time required to access specific bits within said single page on all accesses after an initial page access (called page mode access); b) a memory address circuit for addressing the memory array in accordance with address sequences, the address sequences including memory addresses of the first type, the first type of address sequence being row address sequence, and memory addresses of the second type; c) a logic circuit connected to the memory address circuit and the memory array and operating to control addressing of the memory in accordance with the address sequences, the operation of the logic circuit being modified in accordance with a relative number of sequential matches of the address sequences and a number of sequential mismatches of the address sequences so that page mode access is utilized when the relative number of matches is higher than a predetermined number of matches, and page mode access is not used when the relative number of matches is lower than a predetermined number of matches; d) an address comparator for comparing sequential addresses of a first type for sequential matches; and e) a means of modifying operation of said logic circuit by selectively maintaining addresses of the first type at a state which reduces access time for sequential addresses exhibiting the sequential matches of the first type, wherein the logic circuit is responsive to bus signals so as to permit selection of the number of sequential matches of the first type of addresses or a number of sequential mismatches of the first type of addresses needed to switch between using and not using page mode accesses.

Claim 9

Television display system in which memory is addressed from a memory array by using address sequences in specified patterns, the television display system comprising: a) a memory array addressed by using an address of a first type to select a memory page, and an address of a second type to select specific bits or groups of bits within a specified page, wherein the memory array which can remain within a single page for several successive memory accesses with less time required to access specific bits within said single page on all accesses after an initial page access (called page mode access); b) a memory address circuit for addressing the memory array in accordance with address sequences, the address sequences including memory addresses of the first type, the first type of address sequence being row address sequence, and memory addresses of the second type; c) a logic circuit connected to the memory address circuit and the memory array and operating to control addressing of the memory in accordance with the address sequences, the operation of the logic circuit being modified in accordance with a relative number of sequential matches of the address sequences and a number of sequential mismatches of the address sequences so that page mode access is utilized when the relative number of matches is higher than a predetermined number of matches, and page mode access is not used when the relative number of matches is lower than a predetermined number of matches; d) an address comparator for comparing sequential addresses of a first type for sequential matches; and e) a means of modifying operation of said logic circuit by selectively maintaining addresses of the first type at a state which reduces access time for sequential addresses exhibiting the sequential matches of the first type, wherein the logic circuit is responsive to bus signals so as to permit selection of the number of sequential matches of the first type of addresses or a number of sequential mismatches of the first type of addresses needed to switch between using and not using page mode accesses.

Claim 10

Television display system as described in claim 6, further comprising: a) the memory address circuit including a refresh circuit for refreshing the address sequences; b) refresh address used for RAS only refresh cycles, thereby permitting the logic circuit to monitor the address sequences that will be refreshed and cancel refreshing the address sequences if current address sequences are the same.