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US5159278A
Expired / Lapsed
US
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State machine architecture providing increased resolution of output timing
Assignee: Adelante Technologies BV
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Filing: 1991-04-02
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Granted: 1992-10-27
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Expires: 2011-04-02
Abstract
Abstract A circuit allows for improved flexibility in the timing of device output, for example, from a state machine. Output for the device is placed in a first register. The output is forwarded from the first register to a second register. The first register and the second register are clocked on different edges of a clock signal. A selector selects contents of the first register or contents of the second register as the device output for an external device. The selector may be controlled by the contents of one or more flip-flops. When the device is a state machine, the output of each flip-flop may also be used as feedback to the state machine.
Inventors
- 👤 Phillip E. Mattison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:05
CPC Classifications
G; G06; G06F; G06F7/00
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
226 words
In a device, a circuit for providing for flexibility in timing of providing device output to an input of an external device, the circuit comprising: first register means, including an input and an output, for receiving the device output at the input of the first register means and placing the device output at the output of the first register means; second register means, including an input and an output, the input of the second register means being coupled to the output of the first register means, for receiving the device output from the output of the first register means at the input of the second register means and placing the device output at the output of the second register means; clocking means, coupled to the first register means and the second register means, for clocking the first register means on a first clock edge of a clock signal and clocking the second register means on a second clock edge of the clock signal, wherein the first clock edge does not equal the second clock edge; and, selection means, coupled to the output of the first register means and the output of the second register means, for selecting a first of the output of the first register means and the output of the second register means to be ellectrically coupled to the input of the external device.
Claim 2
Dependent Claim
226 words
In a device, a circuit for providing for flexibility in timing of providing device output to an input of an external device, the circuit comprising: first register means, including an input and an output, for receiving the device output at the input of the first register means and placing the device output at the output of the first register means; second register means, including an input and an output, the input of the second register means being coupled to the output of the first register means, for receiving the device output from the output of the first register means at the input of the second register means and placing the device output at the output of the second register means; clocking means, coupled to the first register means and the second register means, for clocking the first register means on a first clock edge of a clock signal and clocking the second register means on a second clock edge of the clock signal, wherein the first clock edge does not equal the second clock edge; and, selection means, coupled to the output of the first register means and the output of the second register means, for selecting a first of the output of the first register means and the output of the second register means to be ellectrically coupled to the input of the external device.
Claim 3
Dependent Claim
44 words
A device as in claim 1 wherein the device output comprises a plurality of bits; the first register means comprises a flip-flop for each bit of the device output; and, the second register means comprises a flip-flop for each bit of the device output.
Claim 4
Dependent Claim
26 words
A device as in claim 1 wherein the device is a state machine and the device output is coupled to an input of the state machine.
Claim 5
Dependent Claim
52 words
A device as in claim 3 wherein the selection means includes multiplexor means for selecting the first of the output of the first register means and the output of the second register means to be electrically coupled to the input of the external device; and, control means for controlling the multiplexor means.
Claim 6
Dependent Claim
71 words
A device as in claim 4 wherein the state machine includes state logic circuitry, the state logic circuitry having an output, and the control means is a flip-flop which includes an input and an output, the input of the flip-flop being coupled to the output of the state logic circuitry, and the output of the flip-flop being coupled to the multiplexor means and providing a control signal to the multiplexor means.
Claim 7
Dependent Claim
19 words
A device as in claim 5 wherein the control signal is coupled to an input of the state machine.
Claim 8
Dependent Claim
37 words
A device as in claim 4 wherein the device output comprises a plurality of bits; and, the control means comprises a plurality of flip-flops, each flip-flop controlling selection for at least one bit of the device output.
Claim 9
Dependent Claim
26 words
A device as in claim 7 wherein control signals from each flip-flop in the plurality of flip-flops are coupled to an input of the state machine.
Claim 10
Dependent Claim
44 words
A device as in claim 3 wherein the device output comprises a plurality of bits; and, the selection means includes a pair of tri-state gates for each bit of the device output, one of the tri-state gates in each pair having an inverted input.
Claim 11
Dependent Claim
65 words
A device as in claim 9 wherein the state machine includes state logic circuitry, the state logic circuitry having an output, and each of the pairs of tri-state gates is controlled by a flip-flop, an input of the flip-flop being coupled to the output of the state logic circuitry and an output of the flip-flop providing a control signal to each pair of tri-state gates.
Claim 12
Dependent Claim
19 words
A device as in claim 10 wherein each control signal is coupled to an input of the state machine.
Claim 13
Dependent Claim
205 words
A circuit for providing for flexibility in the timing of providing device output from a device to an input of an external device, the circuit comprising for each bit of device output; first flip-flop means, having an input coupled to the device output and having an output, for, at the input of the first flip-flop means, receiving a bit of the device output from the device; second flip-flop means, having an input coupled to the output of the first flip-flop means and having an output, for receiving on the input of the second flip-flop means, the bit of the device output from the output of the first flip-flop means; clocking means for clocking the first flip-flop means on a first clock edge of a clock signal and clocking the second flip-flop means on a second clock edge of the clock signal, wherein the first clock edge does not equal the second clock edge; and, selection means, coupled to the output of the first flip-flop means and to the output of the second flip-flop means, for selecting a first of the output of the first flip-flop means and the output of the second flip-flop means to be electrically coupled to the input of the external device.
Claim 14
Dependent Claim
205 words
A circuit for providing for flexibility in the timing of providing device output from a device to an input of an external device, the circuit comprising for each bit of device output; first flip-flop means, having an input coupled to the device output and having an output, for, at the input of the first flip-flop means, receiving a bit of the device output from the device; second flip-flop means, having an input coupled to the output of the first flip-flop means and having an output, for receiving on the input of the second flip-flop means, the bit of the device output from the output of the first flip-flop means; clocking means for clocking the first flip-flop means on a first clock edge of a clock signal and clocking the second flip-flop means on a second clock edge of the clock signal, wherein the first clock edge does not equal the second clock edge; and, selection means, coupled to the output of the first flip-flop means and to the output of the second flip-flop means, for selecting a first of the output of the first flip-flop means and the output of the second flip-flop means to be electrically coupled to the input of the external device.
Claim 15
Dependent Claim
36 words
A device as in claim 12 wherein the device is state logic circuitry and the bit of the device output received by the first flip-flop means is coupled to an input of the state logic circuitry.
Claim 16
Dependent Claim
25 words
A device as in claim 13 wherein the selection means comprises a pair of tri-state gates, one of the tri-state gates having an inverted input.
Claim 17
Dependent Claim
47 words
A device as in claim 14 wherein the pair of tri-state gates is controlled by a flip-flop, an input of the flip-flop being coupled to an output of the state logic circuitry, and output from the flip-flop providing a control signal to the pair of tri-state gates.
Claim 18
Dependent Claim
20 words
A device as in claim 15 wherein the control signal is coupled to an input of the state logic circuitry.
Claim 19
Independent Claim
100 words
A method for providing flexibility in output timing of a device, for each bit of output, the method comprising the steps of: (a) storing the bit in a first flip-flop; (b) forwarding the bit from the first flip-flop to a second flip-flop; (c) clocking the first flip-flop and the second flip-flop using different edges of a clock signal, wherein the clocking is done simultaneously with steps (a) and (b) and the clocking determines timing for step (b); and, (d) selecting one of the first flip-flop and the second flip-flop to be electrically coupled to an input of an external device.
Claim 20
Independent Claim
100 words
A method for providing flexibility in output timing of a device, for each bit of output, the method comprising the steps of: (a) storing the bit in a first flip-flop; (b) forwarding the bit from the first flip-flop to a second flip-flop; (c) clocking the first flip-flop and the second flip-flop using different edges of a clock signal, wherein the clocking is done simultaneously with steps (a) and (b) and the clocking determines timing for step (b); and, (d) selecting one of the first flip-flop and the second flip-flop to be electrically coupled to an input of an external device.
Claim 21
Dependent Claim
26 words
A method as in claim 17 additionally comprising the step of: (e) providing the bit stored in the first flip-flop to an input of the device.
Claim 22
Independent Claim
65 words
A method as in clam 17 wherein step (d) includes the substeps of: (d.1) sending from the device to a third flip-flop, a control bit; (d.2) sending from the third flip-flop to a selector the control bit; (d.3) selecting by the selector on the basis of the control bit, one of the first flip-flop and the second flip-flop to provide output to an external device.
Claim 23
Independent Claim
65 words
A method as in clam 17 wherein step (d) includes the substeps of: (d.1) sending from the device to a third flip-flop, a control bit; (d.2) sending from the third flip-flop to a selector the control bit; (d.3) selecting by the selector on the basis of the control bit, one of the first flip-flop and the second flip-flop to provide output to an external device.
Claim 24
Dependent Claim
12 words
A method as in claim 19 wherein the selector is a multiplexor.
Claim 25
Dependent Claim
15 words
A method as in claim 19 wherein the selector is a pair of tri-state gates.
Claim 26
Dependent Claim
28 words
A method as in claim 19 wherein the device is a state machine and output from the third flip-flop is connected to an input of the state machine.
Claim 27
Dependent Claim
13 words
A method as in claim 17 wherein the device is a state machine.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-27 | 1996-04-27 | 1996-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-27 | 2000-04-27 | 2000-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-27 | 2004-04-27 | 2004-10-27 | $7700.00 | Window Closed / Lapsed |