Precision tristate output driver circuit having a voltage clamping feature

Claim 2

A tristate output driver circuit (40) comprising: an output terminal (12) having an associated output voltage; a load (18) coupled between the output terminal and a termination voltage source; a first switch (Q7) coupled between a first voltage source and the output terminal, the first switch including a control node; a second switch (Q8) coupled between a second voltage source and the output terminal, the second switch including a control node; means (31) coupled to the control nodes of the first and second switches for simultaneously turning on one of the switches and turning off the other switch to form an on-switch and an off-switch responsive to the polarity of a differential input voltage in a first operational mode; means (35) coupled to the control nodes of the first and second switches for turning off the on-switch in a second operational mode such that both the first and second switches are off; and means (43) having a first input coupled to the output terminal, a second input coupled to the second voltage source, and first and second outputs respectively coupled to the control nodes of the first and second switches for voltage clamping the first and second outputs to a voltage that is equal to the more negative of the output voltage and the second voltage source plus a predetermined voltage.

Claim 3

A tristate output driver circuit as in claim 1 in which the means (31) for simultaneously turning on one of the switches and turning off the other of the switch comprises: a first differential pair of transistors (Q1, Q2) having a differential input for receiving the differential input voltage, a differential output formed of first and second single-ended outputs respectively coupled to the control nodes of the first and second switches, and a source node; bias means (36) coupled to the source node; and load means (32, 34) coupled to the differential output.

Claim 4

A tristate output driver circuit as in claim 2 in which the first differential pair of transistors (Q1, Q2) includes a cascode output stage (Q17, Q18).

Claim 5

A tristate output driver circuit as in claim 2 in which the load means (32, 34) comprises first and second equal-valued bootstrapped load current sources (60) respectively coupled to the first and second single-ended outputs.

Claim 6

A tristate output driver circuit as in claim 2 in which the bias means (36) comprises a cascoded tail current source (Q19, Q20).

Claim 7

A tristate output driver circuit as in claim 2 in which the load means (32, 34) comprises first and second equal-valued bootstrapped load current sources (60) respectively coupled to the first and second single-ended outputs and the bias means (36) comprises a cascoded tail current source (Q19, Q20) having a value equal to twice that of one of the first and second load current sources.

Claim 8

A tristate output driver circuit as in claim 1 in which the means (35) for turning off the on-switch comprises: a second differential pair of transistors (Q5, Q6) having a differential input coupled to the differential input of the first differential pair of transistors, a source node, and a differential output cross-coupled to the differential output of the first differential pair of transistors; a third differential pair of transistors (Q3, Q4) having a differential input for receiving a tristate selection voltage, a source node, and a differential output formed of first and second single-ended outputs wherein the first single-ended output is coupled to the source node of the second differential pair of transistors and the second single-ended output is coupled to a source of constant voltage; and bias means (37) coupled to the source node of the third differential pair of transistors.

Claim 9

A tristate output driver circuit as in claim 7 in which the bias means (37) comprises a cascoded tail current source (Q21, Q22).

Claim 10

A tristate output driver circuit as in claim 1 in which the means (43) for voltage clamping comprises: a bias node; a first voltage clamp (46, 56, D3) having an input forming the first input of the voltage clamping means and an output coupled to the bias node; a second voltage clamp (48, 58, D4) having an input forming the second input of the voltage clamping means and an output coupled to the bias node; a first diode (D6) coupled between the bias node and the first output of the voltage clamping means; a second diode (D5) coupled between the bias node and the second output of the voltage clamping means; and a bias current source (39) coupled to the bias node.

Claim 11

A tristate output driver circuit as in claim 9 in which each of the first and second voltage clamps comprise: a unity gain buffer amplifier (46, 48) having an input forming the input of the voltage clamp and an output; a diode (D3, D4) having a cathode and an anode forming the output of the voltage clamp; and voltage dropping means (56, 58) coupled between the output of the unity gain buffer amplifier and cathode of the diode.

Claim 12

A tristate output driver circuit (30) comprising: an output terminal (12) having an associated output voltage; a load (18) coupled between the output terminal and a termination voltage source; a first switch (Q7) coupled between a first voltage source and the output terminal, the first switch including a control node; a second switch (Q8) coupled between a second voltage source and the output terminal, the second switch including a control node; means (31) coupled to the control nodes of the first and second switches for simultaneously turning on one of the switches and turning off the other switch to form an on-switch and an off-switch responsive to the polarity of a differential input voltage in a first operational mode; means (35) coupled to the control nodes of the first and second switches for turning off the on-switch in a second operational mode such that both the first and second switches are off; first means (41) having a first input coupled to the first voltage source, a second input coupled to the output terminal, and an output coupled to the control node of the first switch for voltage clamping the output to a voltage that is equal to the more negative of the output voltage and the first voltage source plus a predetermined voltage; and second means (43) having a first input coupled to the output terminal, a second input coupled to the second voltage source, and an output coupled to the control node of the second switch for voltage clamping the output to a voltage that is equal to the more negative of the output voltage and the second voltage source plus a predetermined voltage.

Claim 13

A tristate output driver circuit (30) comprising: an output terminal (12) having an associated output voltage; a load (18) coupled between the output terminal and a termination voltage source; a first switch (Q7) coupled between a first voltage source and the output terminal, the first switch including a control node; a second switch (Q8) coupled between a second voltage source and the output terminal, the second switch including a control node; means (31) coupled to the control nodes of the first and second switches for simultaneously turning on one of the switches and turning off the other switch to form an on-switch and an off-switch responsive to the polarity of a differential input voltage in a first operational mode; means (35) coupled to the control nodes of the first and second switches for turning off the on-switch in a second operational mode such that both the first and second switches are off; first means (41) having a first input coupled to the first voltage source, a second input coupled to the output terminal, and an output coupled to the control node of the first switch for voltage clamping the output to a voltage that is equal to the more negative of the output voltage and the first voltage source plus a predetermined voltage; and second means (43) having a first input coupled to the output terminal, a second input coupled to the second voltage source, and an output coupled to the control node of the second switch for voltage clamping the output to a voltage that is equal to the more negative of the output voltage and the second voltage source plus a predetermined voltage.

Claim 14

A tristate output driver circuit as in claim 11 in which the means (31) for simultaneously turning on one of the switches and turning off the other of the switch comprises: a first differential pair of transistors (Q1, Q2) having a differential input for receiving the differential input voltage, a differential output formed of first and second single-ended outputs respectively coupled to the control nodes of the first and second switches, and a source node; bias means (36) coupled to the source node; and load means (32, 34) coupled to the differential output.

Claim 15

A tristate output driver circuit as in claim 12 in which the first differential pair of transistors (Q1, Q2) includes a cascode output stage (Q17, Q18).

Claim 16

A tristate output driver circuit as in claim 12 in which the load means (32, 34) comprises first and second equal-valued bootstrapped load current sources (60) respectively coupled to the first and second single-ended outputs.

Claim 17

A tristate output driver circuit as in claim 12 in which the bias means (36) comprises a cascoded tail current source (Q19, Q20).

Claim 18

A tristate output driver circuit as in claim 12 in which the load means (32, 34) comprises first and second equal-valued bootstrapped load current sources (60) respectively coupled to the first and second single-ended outputs and the bias means (36) comprises a cascoded tail current source (Q19, Q20) having a value equal to twice that of one of the first and second load current sources.

Claim 19

A tristate output driver circuit as in claim 11 in which the means (35) for turning off the on-switch comprises: a second differential pair of transistors (Q5, Q6) having a differential input coupled to the differential input of the first differential pair of transistors, a source node, and a differential output cross-coupled to the differential output of the first differential pair of transistors; a third differential pair of transistors (Q3, Q4) having a differential input for receiving a tristate selection voltage, a source node, and a differential output formed of first and second single-ended outputs wherein the first single-ended output is coupled to the source node of the second differential pair of transistors and the second single-ended output is coupled to a source of constant voltage; and bias means (37) coupled to the source node of the third differential pair of transistors.

Claim 20

A tristate output driver circuit as in claim 17 in which the bias means (37) comprises a cascoded tail current source (Q21, Q22).

Claim 21

A tristate output driver circuit as in claim 11 in which the first and second means (41, 43) for voltage clamping each comprise: a bias node; a first voltage clamp (42, 52, D1; 46, 56, D3) having an input forming the first input of the voltage clamping means and an output coupled to the bias node; a second voltage clamp (44, 54, D2; 48, 58, D4) having an input forming the second input of the voltage clamping means and an output coupled to the bias node; a diode (D6, D5) coupled between the bias node and the output of the voltage clamping means; and a bias current source (38, 39) coupled to the bias node.

Claim 22

A tristate output driver circuit as in claim 19 in which each of the first and second voltage clamps comprise: a unity gain buffer amplifier (42-48) having an input forming the input of the voltage clamp and an output; a diode (D1-D4) having a cathode and an anode forming the output of the voltage clamp; and voltage dropping means (52-58) coupled between the output of the unity gain buffer amplifier and cathode of the diode.

Claim 25

A method for providing a tristate output as in claim 21 including the step of voltage clamping the control node of the off-switch in the first operational mode to a voltage that is equal to the more negative of the first voltage source and the output voltage plus a predetermined voltage when the off-switch is the first switch and to a voltage that is equal to the more negative of the second voltage source and the output voltage plus a predetermined voltage when the off-switch is the second switch.

Claim 28

A method for providing a tristate output as in claim 23 including the step of voltage clamping the control node of the off-switch in the first operational mode to a voltage that is equal to the more negative of the second voltage source and the output voltage plus a predetermined voltage.