Tri-state logic level converter circuit

Claim 1

A circuit for converting logic levels between logic of the type utilizing pairs of emitter-coupled transistors (ECL, CML) and logic of the transistor-transistor type (TTL), comprising a differential input state which includes at least one first transistor (T 1 ) and one second transistor (T 2 ) whose emitters are coupled, a principal current source (I 1 ) which is connected between said coupled emitters, and a negative supply voltage source, the collectors of said first and second transistors being connected to a positive supply voltage source by a first resistor (R 1 ) and a second resistor (R 2 ), respectively, the base of the first transistor being coupled to a reference voltage (V REF ) and the base of the second transistor being coupled to an input signal (E 1 ) whose level is to be translated, a first diode (D 1 ) and a second diode (D 2 ) whose anodes are connected to ground and whose cathodes are connected to the collector of the first transistor and the second transistor, respectively, and also comprising an output stage which includes a fifth transistor (T 5 ) and a sixth transistor (T 6 ) whose collector-emitter paths are connected in series, the emitter of the fifth transistor being connected to ground, its base being connected to the collector of the first transistor and its collector being connected to the emitter of the sixth transistor at a point which forms the output of converter circuit, the base of the sixth transistor being connected to the collector of the second transistor and its collector being connected to the positive supply voltage source, characterized in that in order to realize a third output state having a high output impedance, the converter circuit further comprises a seventh transistor (T 7 ) and an eighth transistor (T 8 ) whose emitters are coupled together and connected to the collector of a ninth transistor (T 9 ) whose base is connected to the base of the second transistor (T 2 ) and whose emitter is connected to the emitters of the first transistor (T 1 ) and the second transistor (T 2 ), the base of the seventh transistor (T 7 ) receiving said reference voltage and the collector of the seventh transistor (T 7 ) being connected to ground, the base of the eighth transistor (T 8 ) being connected to the base of a tenth transistor (T 10 ) which constitutes a selection input (E 2 ) for said third state, the collector and emitter of the tenth transistor being connected to ground and coupled to the base of the second transistor (T 2 ), respectively, the collector of the eighth transistor (T 8 ) being connected to the collector of the second transistor (T 2 ), and a third diode (D 3 ) whose anode is connected to the base of the fifth transistor (T 5 ) and whose cathode is connected to the collector of the second transistor (T 2 ).