Extreme level circuit

Claim 2

An extreme level circuit for detecting an extreme level of two input signals, comprising: a differential circuit wherein a pair of differential transistors are connected their emitters with each other and a common current source is connected to the emitter junction node of the differential transistors; a pair of emitter follower transistors coupled to the differential circuit for applying the input signals to the bases of the differential transistors; and a pair of bias generating circuits each coupled in series with one of the emitter follower circuits, wherein each bias generating circuit has a bias transistor whose base being connected to a fixed bias source and a current source connected in series with the bias transistor; and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors.

Claim 3

An extreme level circuit of claim 1, wherein the current source in each of the bias generating circuits includes a resistor.

Claim 4

An extreme level circuit of claim 1, wherein the extreme level circuit includes bipolar transistors for the differential transistors, emitter follower transistors and the bias generating transistors.

Claim 5

An extreme level circuit of claim 1, wherein the extreme level circuit includes field effect transistors for the differential transistors, emitter follower transistors and the bias generating transistors.

Claim 6

An extreme level circuit for detecting an extreme level of two input signals, comprising: a first differential circuit wherein a first differential transistor connected its base to one of the input signals and a second differential transistor are connected their emitters with each other and a first current source is connected between a first reference potential source and the emitter junction node of the first and second differential transistors; a first active load circuit which is connected between a second reference potential source and the collectors of the first and second differential transistors of the first differential circuit; a second differential circuit wherein a third differential transistor connected its base to the other of the input signals and a fourth differential transistor connected its base to the base of the second differential transistor are connected their emitters with each other and a second current source is connected to the first reference potential source and the emitter junction node of the third and fourth differential transistors; a second active load circuit which is connected between the second reference potential source and the collectors of the third and fourth differential transistors of the second differential circuit; a third current source connected between the first reference potential source and the base junction node of the second and fourth differential transistors; a first feedback transistor connected its base-emitter path in parallel with the collector-base path of the second differential transistor and its collector to the second reference potential source; and a second feedback transistor connected its base-emitter path in parallel with the collector-base path of the fourth differential transistor and its collector to the second reference potential source.

Claim 7

An extreme level circuit for detecting an extreme level of two input signals, comprising: a first differential circuit wherein a first differential transistor connected its base to one of the input signals and a second differential transistor are connected their emitters with each other and a first current source is connected between a first reference potential source and the emitter junction node of the first and second differential transistors; a first active load circuit which is connected between a second reference potential source and the collectors of the first and second differential transistors of the first differential circuit; a second differential circuit wherein a third differential transistor connected its base to the other of the input signals and a fourth differential transistor connected its base to the base of the second differential transistor are connected their emitters with each other and a second current source is connected to the first reference potential source and the emitter junction node of the third and fourth differential transistors; a second active load circuit which is connected between the second reference potential source and the collectors of the third and fourth differential transistors of the second differential circuit; a third current source connected between the first reference potential source and the base junction node of the second and fourth differential transistors; a first feedback transistor connected its base-emitter path in parallel with the collector-base path of the second differential transistor and its collector to the second reference potential source; and a second feedback transistor connected its base-emitter path in parallel with the collector-base path of the fourth differential transistor and its collector to the second reference potential source.

Claim 8

An extreme level circuit of claim 5, wherein each of the first and second active load circuits include a current mirror circuit.

Claim 9

An extreme level circuit of claim 5, wherein each of the first and second active load circuits include a bias transistor having a base connected to a fixed bias source.

Claim 10

An extreme level circuit of claim 5, further comprising: a first cross feedback transistor connected its base to the base of the first feedback transistor and its collector-emitter path between the second reference potential source and the collector of the fourth differential transistor; and a second cross feedback transistor connected its base to the base of the second feedback transistor and its collector-emitter path between the second reference potential source and the collector of the second differential transistor.

Claim 11

An extreme level circuit of claim 8, wherein each of the first and second active load circuits include a current mirror circuit.

Claim 12

An extreme level circuit of claim 8, wherein each of the first and second active load circuits include a bias transistor having a base connected to a fixed bias source.