US4625131A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Attenuator circuit
Assignee: US Philips Corp
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Filing: 1984-03-16
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Granted: 1986-11-25
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Expires: 2004-03-16
Abstract
Abstract A frequency-to-phase converter comprises an attenuator circuit (1), a delay circuit (2) and a comparator (3). The attenuator circuit (1) is provided with two transistors (T 1 , T 2 ), which are arranged as a differential pair and whose collectors (9, 10) are coupled to the positive supply-voltage terminal (5). A voltage divider (R x , R y ) with a tap (11) is arranged between the collectors (9, 10). If a signal is applied to the input terminal (4), the attenuated signal is available on the tap (11) and the unattenuated signal is available on the collector (9). The attenuated signal is applied to input (20) through an emitter-follower (T 4 ) and the unattenuated signal is applied to input (21) of the comparator (3) through an emitter-follower (T 3 ) and a delay circuit (2). A signal, whose different frequencies are delayed by the same time over a wide frequency range appears on the output (22).
Inventors
- 👤 Wolfdietrich G. Kasperkovitz
- 👤 Dirk J. Dullemond
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:46
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/54
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
144 words
A circuit for providing an attenuated electric signal and an unattenuated reference signal with related d.c. reference levels comprising: first and second transistors connected to provide differential currents from a common current source, one of said transistors connected to receive an input electric signal to be attenuated; first and second load impedances connected to each of said transistors for providing a return path for said differential currents through a connected voltage source; a voltage divider connected between the junctions of said load impedances and transistors, said voltage divider having a common tap; and third and fourth current amplifiers connected to said tap and one of said voltage divider ends, said current amplifiers providing said attenuated signal proportional to said input electric signal and said unattenuated signal proportional to said input electric signal, said attenuated and unattenuated signals having d.c. levels which are substantially equal.
Claim 2
Dependent Claim
144 words
A circuit for providing an attenuated electric signal and an unattenuated reference signal with related d.c. reference levels comprising: first and second transistors connected to provide differential currents from a common current source, one of said transistors connected to receive an input electric signal to be attenuated; first and second load impedances connected to each of said transistors for providing a return path for said differential currents through a connected voltage source; a voltage divider connected between the junctions of said load impedances and transistors, said voltage divider having a common tap; and third and fourth current amplifiers connected to said tap and one of said voltage divider ends, said current amplifiers providing said attenuated signal proportional to said input electric signal and said unattenuated signal proportional to said input electric signal, said attenuated and unattenuated signals having d.c. levels which are substantially equal.
Claim 3
Dependent Claim
33 words
The circuit of claim 1 further comprising a delay circuit connected to receive said unattenuated signal; and a comparator connected to receive a delayed signal from said delay circuit, and said attenuated signal.
Claim 4
Dependent Claim
36 words
The circuit of claim 1 wherein said third and fourth current amplifiers include third and fourth bipolar transistors connected as emitter followers, having control electrodes connected to said voltage divider tap and one voltage divider end.
Claim 5
Dependent Claim
63 words
An attenuator circuit as claimed in claim 3, wherein first and second current sources are connected in emitters of the third and fourth transistors, the ratio between the currents supplied by said sources being such that a d.c. level on the tap for the attenuated signal is substantially equal to a d.c. level on the one divider end which carries the unattenuated signal.
Claim 6
Dependent Claim
40 words
An attenuator circuit as claimed in claim 4, wherein the ratio between the emitter areas of the third and the fourth transistor is substantially equal to the ratio between the currents in the emitter of the third and fourth transistors.
References Cited (Backward Citations)
US3522443A
Cited
US3778646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-24 | 1990-05-26 | 1990-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-24 | 1994-05-26 | 1994-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-24 | 1998-05-26 | 1998-11-25 | $7700.00 | Window Closed / Lapsed |