Patent US4099559A successfully refreshed from Google Patents.
Patent US5157286A successfully refreshed from Google Patents.
US5157286A
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US
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Conditional clocking of the second latch of a shift register ratch
Assignee: International Business Machines Corp
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Filing: 1990-02-23
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Granted: 1992-10-20
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Expires: 2010-02-23
Abstract
Abstract A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in response to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
Inventors
- 👤 Nicholas D. Butler
- 👤 Roy B. Harrison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:03
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/318552; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
270 words
A logic circuit for use with non-overlapping first and second clock signals and a first address signal, said logic circuit comprising in combination: a first register comprising first and second register latches, each of said first and second register latches having a data input, a data output and a clock input, the output of said first register latch being coupled to the input of said second register latch; a first logic gate having a first input for receiving said first address signal and a second input for receiving said first clock signal, the output of said first gate being coupled to the clock input of said first register latch, such that data at the input of said first register latch is clocked into said first register latch when both said first address signal and said first clock signal are active; a first control latch having a data input, a data output and a clock input, said data input receiving said first address signal, and said clock input receiving said first clock signal, such that said first address signal is clocked into said first control latch when said first clock signal is active; a second logic gate having a first input coupled to the output of said first control latch and a second input for receiving said second clock signal, the output of said second gate being coupled to the clock input of said second register latch, such that data at the input of said second register latch is clocked into said second register latch when both the output of said first control latch and said second clock signal are active.
Claim 2
Dependent Claim
270 words
A logic circuit for use with non-overlapping first and second clock signals and a first address signal, said logic circuit comprising in combination: a first register comprising first and second register latches, each of said first and second register latches having a data input, a data output and a clock input, the output of said first register latch being coupled to the input of said second register latch; a first logic gate having a first input for receiving said first address signal and a second input for receiving said first clock signal, the output of said first gate being coupled to the clock input of said first register latch, such that data at the input of said first register latch is clocked into said first register latch when both said first address signal and said first clock signal are active; a first control latch having a data input, a data output and a clock input, said data input receiving said first address signal, and said clock input receiving said first clock signal, such that said first address signal is clocked into said first control latch when said first clock signal is active; a second logic gate having a first input coupled to the output of said first control latch and a second input for receiving said second clock signal, the output of said second gate being coupled to the clock input of said second register latch, such that data at the input of said second register latch is clocked into said second register latch when both the output of said first control latch and said second clock signal are active.
Claim 3
Dependent Claim
255 words
The logic circuit of claim 1, further comprising: a second register comprising third and fourth register latches, each of said third and fourth register latches having a data input, a data output and a clock input, the output of said third register latch being coupled to the input of said fourth register latch; a third logic gate having a first input for receiving a second address signal and a second input for receiving said first clock signal, the output of said third gate being coupled to the clock input of said third register latch, such that data at the input of said third register latch is clocked into said third register latch when both said second address signal and said first clock signal are active; a second control latch having a data input, a data output and a clock input, said data input receiving said second address signal, and said clock input receiving said first clock signal, such that said second address signal is clocked into said second control latch when said first clock signal is active; a fourth logic gate having a first input coupled to the output of said second control register and a second input for receiving said second clock signal, the output of said fourth gate being coupled to the clock input of said fourth register latch, such that data at the input of said fourth register latch is clocked into said fourth register latch when both the output of said second control latch and said second clock signal are active.
Claim 4
Dependent Claim
53 words
The logic circuit of claim 2, further comprising: a first combinational logic network coupled between the output of said second register latch and the input of said first register latch; and a second combinational logic network coupled between the output of said fourth register latch and the input of said third register latch.
Claim 5
Dependent Claim
29 words
The logic circuit of claim 1, further comprising a combinational logic network coupled between the output of said second register latch and the input of said first register latch.
Claim 6
Dependent Claim
284 words
A logic circuit for use with non-overlapping first and second clock signals, a first address signal and a control signal, said logic circuit comprising in combination: a first register comprising first and second register latches, each of said first and second register latches having a data input, a data output and a clock input, the output of said first register latch being coupled to the input of said second register latch; a first logic gate having a first input for receiving said first address signal, a second input for receiving said first clock signal and a third input for receiving said control signal, the output of said first gate being coupled to the clock input of said first register latch, such that data at the input of said first register latch is clocked into said first register latch when all of said first address signal, said first clock signal and said control signal are active; a first control latch having a data input, a data output and a clock input, said data input receiving said first control signal, and said clock input receiving said first clock signal, such that said control signal is clocked into said first control latch when said first clock signal is active; a second logic gate having a first input coupled to the output of said first control latch and a second input for receiving said second clock signal, the output of said second gate being coupled to the clock input of said second register latch, such that data at the input of said second register latch is clocked into said second register latch when both the output of said first control latch and said second clock signal are active.
Claim 7
Dependent Claim
284 words
A logic circuit for use with non-overlapping first and second clock signals, a first address signal and a control signal, said logic circuit comprising in combination: a first register comprising first and second register latches, each of said first and second register latches having a data input, a data output and a clock input, the output of said first register latch being coupled to the input of said second register latch; a first logic gate having a first input for receiving said first address signal, a second input for receiving said first clock signal and a third input for receiving said control signal, the output of said first gate being coupled to the clock input of said first register latch, such that data at the input of said first register latch is clocked into said first register latch when all of said first address signal, said first clock signal and said control signal are active; a first control latch having a data input, a data output and a clock input, said data input receiving said first control signal, and said clock input receiving said first clock signal, such that said control signal is clocked into said first control latch when said first clock signal is active; a second logic gate having a first input coupled to the output of said first control latch and a second input for receiving said second clock signal, the output of said second gate being coupled to the clock input of said second register latch, such that data at the input of said second register latch is clocked into said second register latch when both the output of said first control latch and said second clock signal are active.
Claim 8
Dependent Claim
155 words
The logic circuit of claim 5, further comprising: a second register comprising third and fourth register latches, each of said third and fourth register latches having a data input, a data output and a clock input, the output of said third register latch being coupled to the input of said fourth register latch, the clock input of said second register latch being coupled to the output of said second logic gate; a third logic gate having a first input for receiving a second address signal, a second input for receiving said first clock signal and a third input for receiving said control signal, the output of said third gate being coupled to the clock input of said third register latch, such that data at the input of said third register latch is clocked into said third register latch when all of said second address signal, said first clock signal and said control signal are active;
Claim 9
Dependent Claim
53 words
The logic circuit of claim 6, further comprising: a first combinational logic network coupled between the output of said second register latch and the input of said first register latch; and a second combinational logic network coupled between the output of said fourth register latch and the input of said third register latch.
Claim 10
Dependent Claim
29 words
The logic circuit of claim 5, further comprising a combinational logic network coupled between the output of said second register latch and the input of said first register latch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |