Patent US5157282A successfully refreshed from Google Patents.
US5157282A
Expired / Lapsed
US
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Programmable output driver for integrated circuits
Assignee: Cypress Semiconductor Corp
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Filing: 1991-04-08
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Granted: 1992-10-20
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Expires: 2011-04-08
Abstract
Abstract The present invention minimizes the noise voltage associated with the switching of output driver transistors of integrated cicruits caused by the rapid change in value of the current, expressed by the term di/dt, from the load into the driver transistors through the package leads. The present invention uses a programmable coarse current control (CCC) circuit and a programmable fine current control (FCC) circuit that control the pull-down output transistors. The FCC creates two time periods, after which it prevents the CCC from controlling an output pull-down transistor. The FCC and the CCC are used to reduce the di/dt dependent voltage noise by controlling the slope and the shape of the output voltage pull-down characteristics.
Inventors
- 👤 Randy T. Ong
- 👤 Suresh M. Menon
- 👤 Hang Kwan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
120 words
A programmable output buffer for an integrated circuit having improved noise reduction as a result of sink current from the load into the integrated circuit comprising: a pull-up circuit; a pull-down circuit; said pull-up circuit and said pull-down circuit having a common input line and a common output line; a programmable and fully-static fine current control means included in said pull-down circuit and connected between said common input line and said common output line; a programmable and fully-static coarse current control means included in said pull-down circuit and connected between said common input line and said common output line; whereby signal transitions on said common input line cause controllable transition on said common output line with controllable slope and shape.
Claim 2
Dependent Claim
120 words
A programmable output buffer for an integrated circuit having improved noise reduction as a result of sink current from the load into the integrated circuit comprising: a pull-up circuit; a pull-down circuit; said pull-up circuit and said pull-down circuit having a common input line and a common output line; a programmable and fully-static fine current control means included in said pull-down circuit and connected between said common input line and said common output line; a programmable and fully-static coarse current control means included in said pull-down circuit and connected between said common input line and said common output line; whereby signal transitions on said common input line cause controllable transition on said common output line with controllable slope and shape.
Claim 3
Dependent Claim
43 words
The programmable output buffer of claim 1 where said fine current control means drives at least one output MOS transistor connected to said data output line, and said coarse current control means drives an output bipolar transistor connected to said common output line.
Claim 4
Dependent Claim
31 words
The programmable output buffer of claim 1 where said fine current control means includes at least one programmable input that retains its logical state by means of a storage cell element.
Claim 5
Dependent Claim
118 words
The programmable output buffer of claim 1 where said fine current control means comprising: a first fully-static delay generator means having a) a first input connected to said data input line, b) a first output connected to a second fully-static delay generator means, c) a second output connected to said second delay generator means and to a first MOS transistor that is connected to said data output line; and said second delay generator means having a) a second input connected to said first output, b) a third output connected to a second MOS transistor that is connected to said data output line, and said third output is also connected to an input of said coarse current control means.
Claim 6
Dependent Claim
35 words
The programmable output buffer of claim 4 where said fine current control means further includes at least one programmable input that determines the length of delay through said first and said second delay generator means.
Claim 7
Dependent Claim
26 words
The programmable output buffer of claim 5 where said programmable input controls the current between a power rail and said first and said second delay means.
Claim 8
Dependent Claim
22 words
The programmable output buffer of claim 6 where said current flow through MOS transistors whose gates are connected to said programmable inputs.
Claim 9
Dependent Claim
87 words
The programmable output buffer of claim 1 where said coarse current control means comprises: a darlington circuit with a bipolar transistor connected to an output of a logic gate; a first input connected to a first input of said logic gate; a second input connected to a second input of said logic gate; a third input connected to said common input line and to the base of said bipolar transistor of said darlington circuit; and a first output connected to the output node of said bipolar transistor.
Claim 10
Dependent Claim
35 words
The programmable output buffer of claim 8 where said logic gate includes a first input connected to a programmable storage element and a second input connected to an output of said fine current control means.
Claim 11
Dependent Claim
31 words
The programmable output buffer of claim 1 where said coarse current control means includes at least one programmable input that retains its logical state by means of a storage cell element.
Claim 12
Dependent Claim
33 words
The programmable output buffer of claim 8 where said coarse current control means further includes at least one programmable input that determines the value of the maximum current flow through said bipolar transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |