US5155855A
Expired / Lapsed
US
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Multi-cpu system using common memory and having access mediation latch
Assignee: Panasonic Electric Works Co Ltd
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Filing: 1988-10-26
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Granted: 1992-10-13
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Expires: 2008-10-26
Abstract
Abstract A multi-CPU system comprises between a CPU without a control terminal and a common memory: an access mediation latch for temporarily latching data information to be transferred and corresponding address information; and a timing control circuit for controlling the timing of data transfer between the access mediation latch and the common memory in accordance with a mediation signal outputted from a contention mediation terminal of the common memory.
Inventors
- 👤 Yasuo Masuo
- 👤 Masayuki Iwatsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:13
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
168 words
A multi-CPU system using a common memory, wherein data information is mutually transferred between a plurality of CPUs each utilizing a port for performing accessing of said memory, said system comprising: a first CPU with a control terminal, which halts said first CPU's access to said common memory in response to a mediation signal provided to said control terminal; a second CPU without any such control terminal; said common memory for outputting said mediation signal to CPUs without priority when a same address of said common memory is attempted to be accessed by a plurality of CPUs; an access mediation latch connected to both said second CPU and said common memory, for temporarily latching data information to be transferred between said second CPU and said common memory and a corresponding address information; and a timing control circuit connected to both said second CPU and said common memory, for controlling timing of data transfer between said access mediation latch and said common memory in accordance with said mediation signal.
Claim 2
Dependent Claim
168 words
A multi-CPU system using a common memory, wherein data information is mutually transferred between a plurality of CPUs each utilizing a port for performing accessing of said memory, said system comprising: a first CPU with a control terminal, which halts said first CPU's access to said common memory in response to a mediation signal provided to said control terminal; a second CPU without any such control terminal; said common memory for outputting said mediation signal to CPUs without priority when a same address of said common memory is attempted to be accessed by a plurality of CPUs; an access mediation latch connected to both said second CPU and said common memory, for temporarily latching data information to be transferred between said second CPU and said common memory and a corresponding address information; and a timing control circuit connected to both said second CPU and said common memory, for controlling timing of data transfer between said access mediation latch and said common memory in accordance with said mediation signal.
Claim 3
Dependent Claim
64 words
A multi-CPU system as claimed in claim 1, wherein said second CPU comprises control means for detecting, from an output signal of said timing control circuit, if transfer of said data information, said address information corresponding to said data information which is latched in said access mediation latch, has been completed, and prohibiting next access to said common memory until completion of said transfer.
Claim 4
Dependent Claim
168 words
A multi-CPU system using a common memory, wherein data information is mutually transferred between a plurality of CPUs each utilizing a port for performing accessing of said memory, said system comprising: said plurality of CPUs being of a non-controllable type in that each said CPU does not contain a control terminal which can be used for halting said CPU's access to said common memory; said common memory for outputting a mediation signal to said CPUs without priority when a same address of said common memory is attempted to be accessed by a plurality of said CPUs; a separate access mediation latch connected between each of said CPUs and said common memory, for temporarily latching data information to be transferred between said CPU and said common memory and a corresponding address information; and a separate timing control circuit connected between each of said CPUs and said common memory, for controlling timing of data transfer between said access mediation latch and said common memory in accordance with said mediation signal.
Claim 5
Dependent Claim
168 words
A multi-CPU system using a common memory, wherein data information is mutually transferred between a plurality of CPUs each utilizing a port for performing accessing of said memory, said system comprising: said plurality of CPUs being of a non-controllable type in that each said CPU does not contain a control terminal which can be used for halting said CPU's access to said common memory; said common memory for outputting a mediation signal to said CPUs without priority when a same address of said common memory is attempted to be accessed by a plurality of said CPUs; a separate access mediation latch connected between each of said CPUs and said common memory, for temporarily latching data information to be transferred between said CPU and said common memory and a corresponding address information; and a separate timing control circuit connected between each of said CPUs and said common memory, for controlling timing of data transfer between said access mediation latch and said common memory in accordance with said mediation signal.
Claim 6
Dependent Claim
63 words
A multi-CPU system as claimed in claim 3, wherein said CPU comprises control means for detecting, from the output signal of said timing control circuit, if transfer of said data information, said address information corresponding to said data information which is latched in said access mediation latch, has been completed, and prohibiting next access to said common memory until completion of said transfer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-13 | 1996-04-13 | 1996-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-13 | 2000-04-13 | 2000-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-13 | 2004-04-13 | 2004-10-13 | $7700.00 | Window Closed / Lapsed |