US4631667A
Expired / Lapsed
US
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Asynchronous bus multiprocessor system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1983-06-27
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Granted: 1986-12-23
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Expires: 2003-06-27
Abstract
Abstract An asynchronous bus multiprocessor system where a plurality of microprogrammed processors communicate with a working memory through a common bus. Microinstructions are read out from working memory. At least one of the processors, in addition to conventional bus interface registers for latching of data, address and commands to be forwarded to the working memory through the bus, is provided with an additional interface register, devoted to the latching of a microinstruction address for a microinstruction to be read out from the working memory. The system is further provided with a multiplexer for selectively loading a microinstruction register either from a microprogram control memory or from the system common bus, via a direct path established between the system common bus and an input set of the multiplexer. The microinstruction transfer speed from working memory to the processor is further enhanced by means of different timing for the data transfer through the bus and the microinstruction transfer through the bus. In the case of data transfer a bus access cycle is started at the end of the processor cycle during which the relevant bus interface register is loaded. In the case of microinstruction read out from working memory, the additional interface register is loaded at the beginning of a processor cycle concurrently with the request of bus access cycle, so that the two overlap.
Inventors
- 👤 Ferruccio Zulian
- 👤 Vittorio Zanchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:40
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
296 words
An improved asynchronous bus multiprocessor system of the type in which a plurality of processors communicate with a working memory through a common system bus wherein each processor comprises: a first bus interface register for the latching of working memory address/commands through an internal bus, a second bus interface register for the latching of information read out from working memory through the internal bus, a microprogrammed control unit comprising: a microprogram memory, a microprogram memory address register having outputs connected to address inputs of said microprogram memory, a microinstruction register for the latching of a microinstruction read out from said microprogram memory, a first loading path from the output of said microprogram memory to the input of said microinstruction register, a decoder for microcommand generation from said microinstruction and a timing unit, wherein the improvement consists in that at least one said processor comprises: a third bus interface register the output of which is coupled to the system bus via the internal bus for the latching of working memory address/commands, having inputs connected to the outputs of said microprogram memory address register; a second loading path for said microinstruction register from said working memory through said system bus to the input of said microinstruction register; gate means inserted on said first and second paths to control information flow on said paths; a logical sequencing network which, clocked by said timing unit, when enabled by an information identifying a microinstruction addressed by said microprogram memory address register as stored in working memory, generates a sequence of microcommands, said microcommands controlling the accesss to said working memory by inhibiting said first and second interface registers and controlling said gate means to inhibit said first loading path and further enabling said third interface register and said second loading path.
Claim 2
Dependent Claim
296 words
An improved asynchronous bus multiprocessor system of the type in which a plurality of processors communicate with a working memory through a common system bus wherein each processor comprises: a first bus interface register for the latching of working memory address/commands through an internal bus, a second bus interface register for the latching of information read out from working memory through the internal bus, a microprogrammed control unit comprising: a microprogram memory, a microprogram memory address register having outputs connected to address inputs of said microprogram memory, a microinstruction register for the latching of a microinstruction read out from said microprogram memory, a first loading path from the output of said microprogram memory to the input of said microinstruction register, a decoder for microcommand generation from said microinstruction and a timing unit, wherein the improvement consists in that at least one said processor comprises: a third bus interface register the output of which is coupled to the system bus via the internal bus for the latching of working memory address/commands, having inputs connected to the outputs of said microprogram memory address register; a second loading path for said microinstruction register from said working memory through said system bus to the input of said microinstruction register; gate means inserted on said first and second paths to control information flow on said paths; a logical sequencing network which, clocked by said timing unit, when enabled by an information identifying a microinstruction addressed by said microprogram memory address register as stored in working memory, generates a sequence of microcommands, said microcommands controlling the accesss to said working memory by inhibiting said first and second interface registers and controlling said gate means to inhibit said first loading path and further enabling said third interface register and said second loading path.
Claim 3
Dependent Claim
34 words
An asynchronous bus multiprocessor system as recited in claim 1 wherein inputs to said third interface register are connected to a permanent code source, the code being representative of working memory read out commands.
Claim 4
Dependent Claim
64 words
An asynchronous bus multiprocessor system as recited in claim 1, wherein said at least one of said processors includes a third loading path of said microinstruction register through third gate means, a set of electrical signals permanently present in input to said third microinstruction code, which, once executed, does not cause any modification in the status of said at least one of said processors.
Claim 5
Dependent Claim
78 words
An asynchronous bus multiprocessor system as recited in claim 3 wherein said gate means on said first, second and third path consist of a multiplexer having its input sets connected to said first, second and third paths, the outputs of said multiplexer being connected to the inputs of said microinstruction register, said sequence of microcommands controlling said multiplexer to disconnect said first path from said third path and said second path to said multiplexer output at subsequent times.
Claim 6
Dependent Claim
97 words
An asynchronous bus multiprocessor system as recited in claim 3 wherein said logical sequencing network includes two flip-flops for the timed generation of two microcommand sets, the first of said sets enabling the loading of said microinstruction register from said third path, the second of said sets enabling a signal of memory access request to be sent to said working memory for starting a memory cycle and, at the end of the memory cycle, through which a microinstruction is read out from said working memory bus, enabling the loading of said microinstruction register from said second path.
Claim 7
Dependent Claim
77 words
An asynchronous bus multiprocessor system as recited in claim 3 wherein said one processor further includes control means for selectively requesting access to said common system bus, either at the end of a processor cycle during which said first interface register is loaded with working memory access information and commands, or at the beginning of a processor cycle next to the one during which said third interface register is loaded with working memory access information and command.
References Cited (Backward Citations)
US3949372A
Cited
US4302808A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-22 | 1990-06-23 | 1990-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-22 | 1994-06-23 | 1994-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-22 | 1998-06-23 | 1998-12-23 | $7700.00 | Window Closed / Lapsed |