Circuit and method of resetting a master/slave flipflop

Claim 2

A flipflop circuit, comprising: a differential transistor input stage having first and second inputs and first and second outputs, said first input receiving a data signal, said second input receiving a reference signal, said first and second outputs developing first and second output signals having opposite logic states at first and second nodes respectively; first means coupled to said first and second nodes for latching said logic states of said first and second output signals at said first and second nodes respectively, said first means including, (a) first current supply means having an output at a third node for providing a first current of predetermined magnitude, (b) a first transistor having a base, a collector, and an emitter, said base being coupled to said second node, said collector being coupled to said first node, (c) a second transistor having a base, a collector, and an emitter, said base being coupled to said first node, said collector being coupled to said second node, and (d) a third transistor having a base, a collector, and an emitter, said base receiving a buffered clock signal, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said third node; and second means coupled to said second node for reducing said second output signal upon receiving a reset signal such that said first means establishes a logic low state at said second node and a logic high state at said first node, said second means including, (e) a fourth transistor having a base, a collector, and an emitter, said base receiving said reset signal, said collector being coupled to said second node, (f) a fifth transistor having a base, a collector, and an emitter, said base and collector being coupled together to said emitter of said fourth transistor, and (g) a sixth transistor having a base, a collector, and an emitter, said collector being coupled to said emitter of said fourth transistor, said base being coupled to said emitter of said fifth transistor, said emitter being coupled to said third node.

Claim 3

A flipflop circuit, comprising: a differential transistor input stage having first and second inputs and first and second outputs, said first input receiving a data signal, said second input receiving a reference signal, said first and second outputs developing first and second output signals having opposite logic states at first and second nodes respectively; first means coupled to said first and second nodes for latching said logic states of said first and second output signals at said first and second nodes respectively, said first means including, (a) first current supply means having an output at a third node for providing a first current of predetermined magnitude, (b) a first transistor having a base, a collector, and an emitter, said base being coupled to said second node, said collector being coupled to said first node, (c) a second transistor having a base, a collector, and an emitter, said base being coupled to said first node, said collector being coupled to said second node, and (d) a third transistor having a base, a collector, and an emitter, said base receiving a buffered clock signal, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said third node; and second means coupled to said second node for reducing said second output signal upon receiving a reset signal such that said first means establishes a logic low state at said second node and a logic high state at said first node, said second means including, (e) a fourth transistor having a base, a collector, and an emitter, said base receiving said reset signal, said collector being coupled to said second node, and (f) a fifth transistor having a base, a collector, and an emitter, said base being coupled to said emitter of said fourth transistor, said collector being coupled to said second node, said emitter being coupled to said third node.

Claim 4

A flipflop circuit, comprising: a differential transistor input stage having first and second inputs and first and second outputs, said first input receiving a data signal, said second input receiving a reference signal, said first and second outputs developing first and second output signals having opposite logic states at first and second nodes respectively; first means coupled to said first and second nodes for latching said logic states of said first and second output signals at said first and second nodes respectively, said first means including, (a) first current supply means having an output at a third node for providing a first current of predetermined magnitude, (b) a first transistor having a base, a collector, and an emitter, said base being coupled to said second node, said collector being coupled to said first node, (c) a second transistor having a base, a collector, and an emitter, said base being coupled to said first node, said collector being coupled to said second node, and (d) a third transistor having a base, a collector, and an emitter, said base receiving a buffered clock signal, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said third node; and second means coupled to said second node for reducing said second output signal upon receiving a reset signal such that said first means establishes a logic low state at said second node and a logic high state at said first node, said second means including, (e) a fourth transistor having a base, a collector, and an emitter, said base receiving said reset signal, said collector being coupled to said second node, and (f) a fifth transistor having a base, a collector, and an emitter, said base being coupled to said emitter of said fourth transistor, said collector being coupled to said second node, said emitter being coupled to said third node.

Claim 5

The flipflop circuit of claim 2 wherein said first means further includes: second current supply means having an output for providing a second current of predetermined magnitude; and a sixth transistor having a base, a collector, and an emitter, said base receiving a first clock signal, said collector being coupled to a first power supply conductor, said emitter being coupled to said output of said second current supply means and to said base of said third transistor for providing said buffered clock signal.

Claim 6

The flipflop circuit of claim 3 wherein said differential transistor input stage includes: a seventh transistor having a base, a collector, and an emitter, said base receiving said data signal, said collector being coupled to said first node; an eighth transistor having a base, a collector, and an emitter, said base receiving a reference signal, said collector being coupled to said second node; a ninth transistor having a base, a collector, and an emitter, said base and collector being coupled together to said first power supply conductor; a first resistor coupled between said emitter of said ninth transistor and said collector of said seventh transistor; a second resistor coupled between said emitter of said ninth transistor and said collector of said eighth transistor; third current supply means having an output for providing a third current of predetermined magnitude; a tenth transistor having a base, a collector, and an emitter, said base receiving a second clock signal, said collector being coupled to said first power supply conductor, said emitter being coupled to said output of said third current supply means; and an eleventh transistor having a base, a collector, and an emitter, said base being coupled to said emitter of said tenth transistor, said collector being coupled to said emitters of said seventh and eighth transistors, said emitter being coupled to said third node.

Claim 7

A flipflop circuit, comprising: a differential transistor input stage having first and second inputs and first and second outputs, said first input receiving a data signal, said second input receiving a reference signal, said first and second outputs developing first and second output signals having opposite logic states at first and second nodes respectively; first and second current supply means each having an output for providing first and second currents of predetermined magnitude respectively; a first transistor having a base, a collector, and an emitter, said base being coupled to said second node, said collector being coupled to said first node; a second transistor having a base, a collector, and an emitter, said base being coupled to said first node, said collector being coupled to said second node; a third transistor having a base, a collector, and an emitter, said base being coupled to said output of said second current supply means, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said output of said first current supply means; a fourth transistor having a base, a collector, and an emitter, said base being coupled to said output of said second current supply means, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said output of said first current supply means; and circuit means coupled between said second node and said output of said first current supply means for reducing said second output signal upon receiving a reset signal such that said first means establishes a logic low state at said second node and a logic high state at said first node, said circuit means including; (a) a fifth transistor having a base, a collector, and an emitter, said base receiving said reset signal, said collector being coupled to said second node, (b) a sixth transistor having a base, a collector, and an emitter, said base and collector being coupled together to said emitter of said fifth transistor, and (c) a seventh transistor having a base, a collector, and an emitter, said base being coupled to said emitter of said sixth transistor, said collector being coupled to said emitter of said fifth transistor, said emitter being coupled to said output of said first current supply means.

Claim 8

A flipflop circuit, comprising: a differential transistor input stage having first and second inputs and first and second outputs, said first input receiving a data signal, said second input receiving a reference signal, said first and second outputs developing first and second output signals having opposite logic states at first and second nodes respectively; first and second current supply means each having an output for providing first and second currents of predetermined magnitude respectively; a first transistor having a base, a collector, and an emitter, said base being coupled to said second node, said collector being coupled to said first node; a second transistor having a base, a collector, and an emitter, said base being coupled to said first node, said collector being coupled to said second node; a third transistor having a base, a collector, and an emitter, said base being coupled to said output of said second current supply means, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said output of said first current supply means; a fourth transistor having a base, a collector, and an emitter, said base being coupled to said output of said second current supply means, said collector being coupled to said emitters of said first and second transistors, said emitter being coupled to said output of said first current supply means; and circuit means coupled between said second node and said output of said first current supply means for reducing said second output signal upon receiving a reset signal such that said first means establishes a logic low state at said second node and a logic high state at said first node, said circuit means including; (a) a fifth transistor having a base, a collector, and an emitter, said base receiving said reset signal, said collector being coupled to said second node, (b) a sixth transistor having a base, a collector, and an emitter, said base and collector being coupled together to said emitter of said fifth transistor, and (c) a seventh transistor having a base, a collector, and an emitter, said base being coupled to said emitter of said sixth transistor, said collector being coupled to said emitter of said fifth transistor, said emitter being coupled to said output of said first current supply means.