US5153725A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic frequency control circuit
Assignee: NEC Electronics Corp
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Filing: 1991-10-07
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Granted: 1992-10-06
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Expires: 2011-10-07
Abstract
Abstract An automatic frequency control circuit includes a phase comparator, a voltage-controlled oscillator, a frequency divider, a decoder, and a discriminating circuit. The phase comparator compares a phase of an input signal of a horizontal sync signal for television with a phase of a signal phase-locked with the horizontal sync signal to generate a control voltage. The VCO outputs a VCO signal having a frequency controlled by the control voltage. The frequency divider divides a frequency of the VCO signal and outputs an intermediate frequency division ratio signal and the phase-locked signal serving as a terminal frequency division ratio output. A decoder logically processes the phase-locked signal, the intermediate frequency division ratio signal, and the VCO signal and outputs a horizontal sync signal phase-locked with the horizontal sync signal. A discriminating circuit triggered at a leading edge of a vertical sync signal for television latches the phase-locked signal and generates an even/odd field discrimination output.
Inventors
- 👤 Yasufumi Masaike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:34
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/10; H04N5/12; H04N5/126
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
161 words
An automatic frequency control circuit comprising: a phase comparator (11) for comparing a phase of an input signal (IH) of a horizontal sync signal for television with a phase of a signal (C) phase-locked with the horizontal sync signal to generate a control voltage; a voltage-controlled oscillator (13) for outputting a voltage-controlled oscillator signal (Y) having a frequency controlled by the control voltage; a frequency divider (14) for dividing a frequency of the voltage-controlled oscillator signal and outputting an intermediate frequency division ratio signal (A, B) and the phase-locked signal serving as a final frequency division ratio output; a decoder (15) for logically processing the phase-locked signal, the intermediate frequency division ratio signal, and the voltage-controlled oscillator signal and outputting a horizontal sync signal phase-locked with the horizontal sync signal; and a discriminating circuit (2), triggered at a leading edge of a vertical sync signal (V) for television, for latching the phase-locked signal and generating an even/odd field discrimination output (F).
Claim 2
Dependent Claim
161 words
An automatic frequency control circuit comprising: a phase comparator (11) for comparing a phase of an input signal (IH) of a horizontal sync signal for television with a phase of a signal (C) phase-locked with the horizontal sync signal to generate a control voltage; a voltage-controlled oscillator (13) for outputting a voltage-controlled oscillator signal (Y) having a frequency controlled by the control voltage; a frequency divider (14) for dividing a frequency of the voltage-controlled oscillator signal and outputting an intermediate frequency division ratio signal (A, B) and the phase-locked signal serving as a final frequency division ratio output; a decoder (15) for logically processing the phase-locked signal, the intermediate frequency division ratio signal, and the voltage-controlled oscillator signal and outputting a horizontal sync signal phase-locked with the horizontal sync signal; and a discriminating circuit (2), triggered at a leading edge of a vertical sync signal (V) for television, for latching the phase-locked signal and generating an even/odd field discrimination output (F).
Claim 3
Dependent Claim
21 words
A circuit according to claim 1, wherein said phase comparator, said voltage-controlled oscillator, and the frequency divider constitute a phase-locked loop.
Claim 4
Dependent Claim
24 words
A circuit according to claim 1, wherein said frequency divider is an 1/8 frequency divider for outputting intermediate 1/2- and 1/4-frequency division ratio signals.
Claim 5
Dependent Claim
36 words
A circuit according to claim 1, wherein said decoder is constituted by a NOR circuit (15) for calculating a logical NOR between the phase-locked signal, the intermediate frequency division ratio signal, and the voltage-controlled oscillator signal.
Claim 6
Dependent Claim
57 words
A circuit according to claim 1, wherein said discriminating circuit is constituted by a discrimination clock generator (21, 22, 23) for generating a discrimination clock at a leading edge of the vertical sync signal using the intermediate frequency division ratio signal and a latch circuit (24) for latching the phase-locked signal in response to the discrimination clock.
Claim 7
Dependent Claim
79 words
A circuit according to claim 5, wherein said discrimination clock generator is constituted by a first flip-flop (21) for reading the vertical sync signal by the intermediate frequency division ratio signal, a second flip-flop (22) for reading a set output of said first flip-flop in response to the intermediate frequency division ratio signal, and an AND circuit (23) for calculating a logical AND between the set output of said first flip-flop and a non-set output of said second flip-flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-06 | 1996-04-06 | 1996-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-06 | 2000-04-06 | 2000-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-06 | 2004-04-06 | 2004-10-06 | $7700.00 | Window Closed / Lapsed |