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US5153698A Expired / Lapsed US ⏱️ 0.0 years remaining

Master slice integrated circuit device

Assignee: Seiko Epson Corp
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Filing: 1990-09-10
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Granted: 1992-10-06
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Expires: 2010-09-10
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Abstract

Abstract In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.

Inventors

  • 👤 Yasuhisa Hirabayashi
  • 👤 Takashi Sakuda
  • 👤 Kazuhiko Okawa
  • 👤 Yasuhiro Oguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 10:21
CPC Classifications
H; H10; H10D; H10D84/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10D84/90; H10W72/00; H10W72/90; H10W72/931; H10W72/932

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 187 words
In a master slice integrated circuit device comprising an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, the improvement comprising intermediate power line connection means conductively connecting each said power line to said main power circuit region, said intermediate connection means comprising, for each said power line, a power branch-off member disposed at a given position on said main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, said power branch-off member and having a predetermined length, so that said connection allowance members for all of said power lines all have substantially the same length, said connection allowance member for each said power line being conductively connected between its associated power branch-off member and the respective power line.
Claim 2
Dependent Claim 187 words
In a master slice integrated circuit device comprising an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, the improvement comprising intermediate power line connection means conductively connecting each said power line to said main power circuit region, said intermediate connection means comprising, for each said power line, a power branch-off member disposed at a given position on said main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, said power branch-off member and having a predetermined length, so that said connection allowance members for all of said power lines all have substantially the same length, said connection allowance member for each said power line being conductively connected between its associated power branch-off member and the respective power line.
Claim 3
Dependent Claim 31 words
A master slice integrated circuit device according to claim 1 wherein said power branch-off member and said connection allowance member for each said power line together form a substantially T-shaped structure.
Claim 4
Dependent Claim 31 words
A master slice integrated circuit device according to claim 1 wherein said power branch-off member and said connection allowance member for each said power line together form a substantially L-shaped structure.
Claim 5
Dependent Claim 30 words
A master slice integrated circuit device according to claim 1 wherein each of said power lines is formed along a boundary formed between an adjacent pair of the internal cells.
Claim 6
Dependent Claim 55 words
A master slice integrated circuit device according to claim 1 wherein said external cells are equispaced from one another by a first spacing, P OUT , and said internal cells are equispaced from one another by a second spacing, P IN , where: j P.sub.OUT ≠k P.sub.IN k>j≧1 where j and k are positive integers.
Claim 7
Dependent Claim 65 words
A master slice integrated circuit device according to claim 1, wherein said external cells are equispaced from one another by a first spacing, P OUT , said internal cells are equispaced from one another by a second spacing, P IN , P OUT >P IN , and the predetermined length of each said connection allowance member is greater than or equal to P IN .
Claim 8
Dependent Claim 65 words
A master slice integrated circuit device according to claim 2, wherein said external cells are equispaced from one another by a first spacing, P OUT , said internal cells are equispaced from one another by a second spacing, P IN , P OUT >P IN , and the predetermined length of each said connection allowance member is greater than or equal to P IN .
Claim 9
Dependent Claim 65 words
A master slice integrated circuit device according to claim 3, wherein said external cells are equispaced from one another by a first spacing, P OUT , said internal cells are equispaced from one another by a second spacing, P IN , P OUT >P IN , and the predetermined length of each said connection allowance member is greater than or equal to P IN .
Claim 10
Dependent Claim 65 words
A master slice integrated circuit device according to claim 4, wherein said external cells are equispaced from one another by a first spacing, P OUT , said internal cells are equispaced from one another by a second spacing, P IN , P OUT >P IN , and the predetermined length of each said connection allowance member is greater than or equal to P IN .
Claim 11
Dependent Claim 35 words
A master slice integrated circuit device according to claim 5, wherein P OUT >P IN , and the predetermined length of each said connection allowance member is greater than or equal to P IN .

References Cited (Backward Citations)

US4523106A Cited
US4611236A Cited
US4811073A Cited
JPS6120349A Cited
US4833520A Cited
EP0703641A2 Cited
EP0704805A2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-10-06 1996-04-06 1996-10-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-10-06 2000-04-06 2000-10-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-10-06 2004-04-06 2004-10-06 $7700.00 Window Closed / Lapsed

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