EP0704805A2
Expired / Lapsed
EP
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Address translation device
Assignee: Toshiba Corp
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Filing: 1995-09-27
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Granted: —
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Expires: 2015-09-27
Abstract
Abstract The address translation device includes a virtual page number register (4) for storing a last-accessed virtual page number, a physical page number register (5) for storing a physical page number corresponding to the virtual page number stored in the virtual page number register (4), and a TLB (translation lookaside buffer) circuit (1) for storing a plurality of relationships between the physical page numbers and the virtual page numbers. First, a comparator (6) compares a new virtual page number (2) with an output of the virtual page number register (4). If the new virtual page number matches the output of the virtual page number register (4), the output of the physical page number register (5) is output through a multiplexer (9) as a physical page number (3). If the new and stored page numbers do not match, on the other hand, a mismatch signal (7) output by the comparator (6) activates the TLB circuit (1) so that the output of the TLB circuit (1) is outputted through a multiplexer (9) as a physical page number (3). Different configurations of the TLB circuit are used in such a way that the processing speed can be secured without reducing the hit ratio of the address translation. Further, the access to the TLB circuit is minimized to save the power consumption.
Inventors
- 👤 Kazutaka Nogami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 10:03
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F2212/00; G06F2212/10; G06F2212/1028; G06F2212/60; G06F2212/608; G06F2212/6082; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
209 words
An address translation device, comprising: a first address translation circuit (1) having a first memory circuit for storing m-sets of corresponding relations between a virtual address and a physical address; a second address translation circuit (4, 5) having a second memory circuit for storing a corresponding relation between a virtual address and a physical address, a most recent virtual address and a physical address corresponding to the most recent virtual address being stored therein, the virtual address stored therein being updated whenever said first address translation circuit (1) executes a translation; and comparing means (6) having a comparator (6) for comparing a new virtual address (2) to be translated with a virtual address stored in said second address translation circuit (4, 5), such that when the new virtual address matches the virtual address stored in the second address translation circuit (4, 5), the new virtual address (2) is translated into a physical address and output by said second address translation circuit (4, 5) without activating said first address translation circuit (1), and when the new virtual address does not match the virtual address stored in the second address translation circuit, the new virtual address (2) is translated into a physical address by activating said first address translation circuit (1).
Claim 2
Dependent Claim
78 words
The address translation device of claim 1, wherein said second address translation circuit (4, 5) has n-units of second storing circuits for storing n-units of virtual addresses from the most recent to an n-th from the most recent, respectively, and wherein said comparing means (6) has n-units of comparators, (6) each corresponding to each of said second storing circuits, for comparing a new virtual address (2) with a virtual address stored in said corresponding second storing circuit, respectively.
Claim 3
Dependent Claim
11 words
The address translation device of claim 2, where n is 1.
Claim 4
Dependent Claim
11 words
The address translation device of claim 2, where n is 2
Claim 5
Dependent Claim
13 words
The address translation device of claim 2, wherein m is larger than n.
Claim 6
Dependent Claim
39 words
The address translation device of clam 2, wherein n-sets of corresponding relations between the virtual address and the physical address stored in said second address translation circuit (4, 5) are also stored in said first address translation circuit (1).
Claim 7
Dependent Claim
105 words
The address translation device of claim 1, further comprising a multiplexer (9) having a first input coupled to receive a translated physical address output by said second address translation circuit (4, 5) and having a second input coupled to receive a translated physical address output by said first address translation circuit (1) when said first address translation circuit (1) is activated, said multiplexer (9) providing a signal from said first input as an output when said comparing means (6) outputs a match signal and said multiplexer (9) providing a signal from said second input as an output when said comparing means outputs a mismatch signal.
Claim 8
Dependent Claim
119 words
The address translation device of claim 2, further comprising a multiplexer (9) having a plurality of first inputs coupled to receive translated physical addresses output by a plurality of the second storing circuits of said second address translation circuit (4, 5), said multiplexer (9) having a second input coupled to receive a translated physical address output by said first address translation circuit (1) when said first address translation circuit (1) is activated, said multiplexer (9) providing a signal from the first input corresponding to a one of the comparators when the one comparator outputs a match signal, and said multiplexer (9) providing a signal from said second input as an output when said comparing means outputs a mismatch signal.
Claim 9
Dependent Claim
21 words
The address translation device of claim 1 or 2, wherein said first address translation circuit (1) is of full associative type.
Claim 10
Dependent Claim
180 words
An address translation device of set associative type comprising: address translating means (12) having a plurality of ways (10a, 11a, 10b, 11b, ...) each storing a corresponding relation between a virtual address and a physical address; control means (16, 15i) having a control circuit (16) for storing an indication of a preceding way most recently hit or entry-registered; comparing means (13i) having a plurality of comparators (13a, 13b, 13c, ...) each corresponding to a one of the ways, each of the comparators comparing a virtual address (2) to be translated with a virtual address stored in the corresponding one way (10i, 11i) and outputting a match signal or a mismatch signal as a comparison result; and said control means activating the comparator corresponding to the preceding way, such that when the comparator outputs a match signal, a physical address of the preceding way is output, and when the comparator outputs a mismatch signal, the comparators corresponding to the other ways are individually activated and a physical address is output from a way corresponding to the comparator outputting the match signal.
Claim 11
Dependent Claim
26 words
The address tranlation device of claim 10, wherein when the comparator outputs a mismatch signal, the comparators corresponding to the other ways are activated in sequence.
Claim 12
Dependent Claim
42 words
The address translation device of claim 10, further comprising a plurality of gating means (15i) each for inputting each physical address from each way, each gating means corresponding to each comparator outputting a physical address therefrom in response to the match signal.
Claim 13
Dependent Claim
175 words
An address translation device of set associative type, comprising: address translating means (12) having a plurality of ways (10a, 11a, 10b, 11b ... ) each for storing a corresponding relation between a virtual address and a physical address; control means (16, 15i) having a control circuit (16), for storing an indication of a preceding way most recently hit or entry-registered; comparing means (13i) having a plurality of comparators (13a, 13b, 13c, ...) each corresponding to a one of the ways, each of the comparators comparing a virtual address (2) to be translated with a virtual address stored in the corresponding one way (10i, 11i) and outputting a match signal or a mismatch signal as a comparison result; and said control means activating the preceding way, such that when the comparator outputs a match signal, a physical address of the preceding way is output, and when the comparator outputs a mismatch signal, the other ways are activated in sequence and a physical address is output from a way corresponding to the comparator outputting the match signal.
Claim 14
Dependent Claim
41 words
The address translation device of claim 13, further comprising a plurality of gating means (15i) each for inputting each physical address from each way, each gain means being turned on to output the physical address therefrom in response to the match.
Claim 15
Dependent Claim
19 words
The address translation device of claim 11 or 14, wherein each of said gating means is a tri-state buffer.
Claim 16
Dependent Claim
42 words
The address translation device of claim 15, wherein an output of each of the comparators is applied to a control terminal of each of said tri-state buffers, so that when the comparator outputs the match signal, the tri-state buffer is turned on.
References Cited (Backward Citations)
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