US5151772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Micron Memory Japan Ltd
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Filing: 1990-11-20
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Granted: 1992-09-29
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Expires: 2010-11-20
Abstract
Abstract A semiconductor integrated circuit device is provided which includes a memory cell array located in a generally central area of a semiconductor substrate with peripheral circuits located at both ends of the semiconductor substrate. A wiring layer is also provided which couples the peripheral circuits to one another. This wiring layer is arranged to have a double-layer structure of first and second aluminum layers which are electrically coupled to one another.
Inventors
- 👤 Yasushi Takahashi
- 👤 Hiromi Matsuura
- 👤 Yoshihisa Koyama
- 👤 Masaya Muranaka
- 👤 Katsutaka Kimura
- 👤 Kazuyuki Miyazawa
- 👤 Masamichi Ishihara
- 👤 Hidetoshi Iwai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
324 words
A semiconductor integrated circuit device comprising: (a) a memory cell array including a plurality of memory cells on a rectangular semiconductor substrate having a pair of opposing longer sides and a pair of opposing shorter sides; (b) a first peripheral circuit adjacent one of said shorter sides and a second peripheral circuit adjacent the other of said shorter sides on said semiconductor substrate, wherein said memory cell array is located between said first and second peripheral circuits; (c) an external terminal to be supplied with a predetermined signal other than a power supply signal, said external terminal being located on said semiconductor substrate; (d) a first wiring coupling said external terminal to said first peripheral circuit to provide said predetermined signal to said first peripheral circuit, wherein said first peripheral circuit includes means for producing a predetermined output signal in response to said predetermined signal; (e) a second wiring coupling said first peripheral circuit to said second peripheral circuit for providing said predetermined output signal of said first peripheral circuit to said second peripheral circuit, wherein said second wiring is located at a region of said substrate other than said memory cell array and extends along one of said longer sides in a peripheral area of said semiconductor substrate between said memory cell array and said one of said longer sides, and (f) a third and a fourth wiring formed on both sides of said second wiring and extending along said second wiring, wherein said second wiring comprises a first conductive layer and a second conductive layer on said first conductive layer, said first and second conductive layers being electrically coupled to each other to provide a reduced resistance to said second wiring along said one of said longer sides of the substrate between said first and second peripheral circuits, and further wherein said third and fourth wirings are single-layer wirings each comprised either of said first conductive layer or said second conductive layer.
Claim 2
Dependent Claim
324 words
A semiconductor integrated circuit device comprising: (a) a memory cell array including a plurality of memory cells on a rectangular semiconductor substrate having a pair of opposing longer sides and a pair of opposing shorter sides; (b) a first peripheral circuit adjacent one of said shorter sides and a second peripheral circuit adjacent the other of said shorter sides on said semiconductor substrate, wherein said memory cell array is located between said first and second peripheral circuits; (c) an external terminal to be supplied with a predetermined signal other than a power supply signal, said external terminal being located on said semiconductor substrate; (d) a first wiring coupling said external terminal to said first peripheral circuit to provide said predetermined signal to said first peripheral circuit, wherein said first peripheral circuit includes means for producing a predetermined output signal in response to said predetermined signal; (e) a second wiring coupling said first peripheral circuit to said second peripheral circuit for providing said predetermined output signal of said first peripheral circuit to said second peripheral circuit, wherein said second wiring is located at a region of said substrate other than said memory cell array and extends along one of said longer sides in a peripheral area of said semiconductor substrate between said memory cell array and said one of said longer sides, and (f) a third and a fourth wiring formed on both sides of said second wiring and extending along said second wiring, wherein said second wiring comprises a first conductive layer and a second conductive layer on said first conductive layer, said first and second conductive layers being electrically coupled to each other to provide a reduced resistance to said second wiring along said one of said longer sides of the substrate between said first and second peripheral circuits, and further wherein said third and fourth wirings are single-layer wirings each comprised either of said first conductive layer or said second conductive layer.
Claim 3
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 1, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 4
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 2, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 1, wherein each of said plurality of memory cells comprises a switching element and an information storing element.
Claim 6
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 4, wherein said switching element is an MISFET and said information storing element is a capacitor, and wherein said MISFET and capacitor are coupled in series with one another.
Claim 7
Dependent Claim
57 words
A semiconductor integrated circuit device according to claim 5, wherein said means for producing a predetermined output signal in said first peripheral circuit includes a plurality of inverters arranged so as to generate a first cock signal, as said predetermined output signal, from a row address strobe signal, as said predetermined signal, supplied to said external terminal.
Claim 8
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 6, wherein said second peripheral circuit has a plurality of inverters arranged so as to generate a second clock signal from said first clock signal.
Claim 9
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 7, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 10
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 8, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 11
Dependent Claim
52 words
A semiconductor integrated circuit device according to claim 1, further comprising: (f) a further external terminal to be supplied with a predetermined level of voltage, said further external terminal being arranged on said semiconductor substrate; and (g) a fifth wiring coupling said further external terminal and said first and second peripheral circuits.
Claim 12
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 10, wherein said predetermined level of voltage is one of a power supply voltage and a reference voltage.
Claim 13
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 11, wherein a part of said fifth wiring comprises said first conductive layer and said second conductive layer, and wherein said first and second conductive layers are electrically coupled to each other.
Claim 14
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 12, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 15
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 13, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 16
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 1, wherein said third and fourth wirings are comprised of said second conductive layer.
Claim 17
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 15, wherein said second conductive layer comprises an aluminum layer.
Claim 18
Dependent Claim
227 words
A semiconductor integrated circuit device comprising: (a) a memory cell array including a plurality of memory cells on a rectangular semiconductor substrate; (b) a first peripheral circuit and a second peripheral circuit on said semiconductor substrate; (c) an external terminal to be supplied with a predetermined signal other than a power supply signal, said external terminal being located on said semiconductor substrate; (d) a first wiring coupling said external terminal to said first peripheral circuit to provide said predetermined signal to said first peripheral circuit, wherein said first peripheral circuit includes means for producing a predetermined output signal in response to said predetermined signal; (e) a second wiring coupling said first peripheral circuit to said second peripheral circuit for providing said predetermined output signal of said first peripheral circuit to said second peripheral circuit; and (f) a third and a fourth wiring formed on both sides of said second wiring and extending along said second wiring, wherein said second wiring comprises a first conductive layer and a second conductive layer on said first conductive layer, said first and second conductive layers being electrically coupled to each other to provide a reduced resistance to said second wiring between said first and second peripheral circuits, and further wherein said third and fourth wirings are single-layer wirings each comprised either of said first conductive layer or said second conductive layer.
Claim 19
Dependent Claim
227 words
A semiconductor integrated circuit device comprising: (a) a memory cell array including a plurality of memory cells on a rectangular semiconductor substrate; (b) a first peripheral circuit and a second peripheral circuit on said semiconductor substrate; (c) an external terminal to be supplied with a predetermined signal other than a power supply signal, said external terminal being located on said semiconductor substrate; (d) a first wiring coupling said external terminal to said first peripheral circuit to provide said predetermined signal to said first peripheral circuit, wherein said first peripheral circuit includes means for producing a predetermined output signal in response to said predetermined signal; (e) a second wiring coupling said first peripheral circuit to said second peripheral circuit for providing said predetermined output signal of said first peripheral circuit to said second peripheral circuit; and (f) a third and a fourth wiring formed on both sides of said second wiring and extending along said second wiring, wherein said second wiring comprises a first conductive layer and a second conductive layer on said first conductive layer, said first and second conductive layers being electrically coupled to each other to provide a reduced resistance to said second wiring between said first and second peripheral circuits, and further wherein said third and fourth wirings are single-layer wirings each comprised either of said first conductive layer or said second conductive layer.
Claim 20
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 17, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 21
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 18, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 22
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 17, wherein each of said plurality of memory cells comprises a switching element and an information storing element.
Claim 23
Dependent Claim
37 words
A semiconductor integrated circuit device according to claim 20, wherein said switching element is a MISFET and said information storing element is a capacitor, and wherein said MISFET and capacitor are coupled in series with one another.
Claim 24
Dependent Claim
57 words
A semiconductor integrated circuit device according to claim 21, wherein said means for producing a predetermined output signal in said first peripheral circuit includes a plurality of inverters arranged so as to generate a first clock signal, as said predetermined output signal, from a row address strobe signal, as said predetermined signal, supplied to said external terminal.
Claim 25
Dependent Claim
33 words
A semiconductor integrated circuit device according to claim 22, wherein said second peripheral circuit has a plurality of inverters arranged so as to generate a second clock signal from said first clock signal.
Claim 26
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 23, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 27
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 24, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 28
Dependent Claim
53 words
A semiconductor integrated circuit device according to claim 17, further comprising: (g) a further external terminal to be supplied with a predetermined level of voltage, said further external terminal being arranged on said semiconductor substrate; and (h) a fifth wiring coupled to said further external terminal and said first and second peripheral circuits.
Claim 29
Dependent Claim
26 words
A semiconductor integrated circuit device according to claim 26, wherein said predetermined level of voltage is one of a power supply voltage and a reference voltage.
Claim 30
Dependent Claim
40 words
A semiconductor integrated circuit device according to claim 27, wherein a part of said fifth wiring comprises said first conductive layer and said second conductive layer, and wherein said first and second conductive layers are electrically coupled to each other.
Claim 31
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 28, wherein said first and second conductive layers are each comprised of an aluminum layer.
Claim 32
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 29, wherein said second conductive layer has a thickness greater than that of said first conductive layer.
Claim 33
Dependent Claim
22 words
A semiconductor integrated circuit device according to claim 17, wherein said third and fourth wirings are comprised of said second conductive layer.
Claim 34
Dependent Claim
18 words
A semiconductor integrated circuit device according to claim 31, wherein said second conductive layer comprises an aluminum layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-29 | 1996-03-30 | 1996-09-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-29 | 2000-03-30 | 2000-09-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-29 | 2004-03-30 | 2004-09-29 | $7700.00 | Window Closed / Lapsed |