Nonvolatile semiconductor memory device with isolated gate electrodes

Claim 2

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a field oxidation film selectively formed on said semiconductor substrate; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said field oxidation film, and a plurality of memory cells formed on said first gate insulating film; wherein each of said plurality of memory cells includes said first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode, and said floating gate electrode and said control gate electrode of each of said plurality of memory cells are isolated from the floating gate electrodes and control gate electrodes of adjacent memory cells, respectively, so as to be formed into islands.

Claim 3

A device according to claim 1, wherein each floating gate electrode and each control gate electrode consists of polysilicon.

Claim 4

A device according to claim 1, wherein each floating gate electrode and each control gate electrode consists of polycide film.

Claim 5

A device according to claim 1, wherein each floating gate electrode and each control gate electrode consists of silicide film.

Claim 6

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a field oxidation film selectively formed on said semiconductor substrate; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said field oxidation film; a plurality of memory cells each comprising a floating gate electrode and a control gate electrode, said floating gate electrode and said control gate electrode of each of said memory cells being isolated from the floating gate electrodes and control gate electrodes of other adjacent memory cells, respectively, so as to be formed into islands; an insulating interlayer formed on said field oxidation film and on said control gate electrodes; contact hole passages extending through said insulating interlayer so as to expose portions of said control gate electrodes; and a plurality of wires, formed on said insulating interlayer, for connecting said control gate electrodes of memory cells of said plurality of memory cells, which are adjacent to each other in a word line direction, through said contact hole passages.

Claim 7

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a field oxidation film selectively formed on said semiconductor substrate; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said field oxidation film; a plurality of memory cells each comprising a floating gate electrode and a control gate electrode, said floating gate electrode and said control gate electrode of each of said memory cells being isolated from the floating gate electrodes and control gate electrodes of other adjacent memory cells, respectively, so as to be formed into islands; an insulating interlayer formed on said field oxidation film and on said control gate electrodes; contact hole passages extending through said insulating interlayer so as to expose portions of said control gate electrodes; and a plurality of wires, formed on said insulating interlayer, for connecting said control gate electrodes of memory cells of said plurality of memory cells, which are adjacent to each other in a word line direction, through said contact hole passages.

Claim 8

A device according to claim 5, wherein each floating gate electrode and each control gate electrode consists of polysilicon.

Claim 9

A device according to claim 5, wherein each floating gate electrode and each control gate electrode consists of polycide film.

Claim 10

A device according to claim 5, wherein said floating gate electrode and said control gate electrode consist of silicide films, respectively.

Claim 11

A device according to claim 5, wherein each wire consists of an aluminum film.

Claim 12

A device according to claim 5, wherein each wire consists of a tungsten film.

Claim 13

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a field oxidation film selectively formed on said semiconductor substrate; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said field oxidation film; a plurality of memory cells each comprising a floating gate electrode and a control gate electrode, said floating gate electrode and aid control gate electrode of each of said memory cells being isolated from the floating gate electrodes and control gate electrodes of other adjacent memory cells, respectively, so as to be formed into islands; a first insulating interlayer formed on said field oxidation film and on said control gate electrodes; first contact hole passages extending through said first insulating interlayer so as to expose portions of said control gate electrodes; a plurality of first wires, formed on said first insulating interlayer, for connecting said control gate electrodes of memory cells of said plurality of memory cells, which are adjacent to each other in a word line direction, through said first contact hole passages; a second insulating interlayer formed on said first insulating interlayer and on said plurality of first wires; a second contact hole passage extending through said second insulating interlayer so as to expose a portion of said plurality of first wires; and a second wire, formed on said second insulating interlayer so as to be in contact with said plurality of first wires through said second contact hole passage, for shunt-connecting said plurality of first wires to each other.

Claim 14

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a field oxidation film selectively formed on said semiconductor substrate; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said field oxidation film; a plurality of memory cells each comprising a floating gate electrode and a control gate electrode, said floating gate electrode and aid control gate electrode of each of said memory cells being isolated from the floating gate electrodes and control gate electrodes of other adjacent memory cells, respectively, so as to be formed into islands; a first insulating interlayer formed on said field oxidation film and on said control gate electrodes; first contact hole passages extending through said first insulating interlayer so as to expose portions of said control gate electrodes; a plurality of first wires, formed on said first insulating interlayer, for connecting said control gate electrodes of memory cells of said plurality of memory cells, which are adjacent to each other in a word line direction, through said first contact hole passages; a second insulating interlayer formed on said first insulating interlayer and on said plurality of first wires; a second contact hole passage extending through said second insulating interlayer so as to expose a portion of said plurality of first wires; and a second wire, formed on said second insulating interlayer so as to be in contact with said plurality of first wires through said second contact hole passage, for shunt-connecting said plurality of first wires to each other.

Claim 15

A device according to claim 11, wherein each floating gate electrode and each control gate electrode consists of polysilicon.

Claim 16

A device according to claim 11, wherein each floating gate electrode and each control gate electrode consists of polycide film.

Claim 17

A device according to claim 11, wherein each floating gate electrode and each control gate electrode consists of silicide film.

Claim 18

A device according to claim 11, wherein said wires each consist of aluminum film.

Claim 19

A device according to claim 11, wherein said wire each consist of tungsten film.

Claim 20

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of field oxidation films selectively formed on said semiconductor substrate; a plurality of memory cells each comprising a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode, formed by sequentially and selectively etching a first insulating film, a first conductive layer, a second insulating film, and a second conductive layer, which are sequentially formed on said semiconductor substrate and on said field oxidation films, so as to expose portions of said field oxidation films; a thermal oxidation film formed by thermally oxidizing upper and side surfaces of said control gate electrodes and side surfaces of said floating gate electrodes; an insulating interlayer formed on said field oxidation films and on said thermal oxidation film; contact hole passages extending through said insulating interlayer so as to expose a portion of each of said control gate electrodes; and a wire, formed on said insulating interlayer, for connecting said control gate electrodes to each other.

Claim 21

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of field oxidation films selectively formed on said semiconductor substrate; a plurality of memory cells each comprising a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode, formed by sequentially and selectively etching a first insulating film, a first conductive layer, a second insulating film, and a second conductive layer, which are sequentially formed on said semiconductor substrate and on said field oxidation films, so as to expose portions of said field oxidation films; a thermal oxidation film formed by thermally oxidizing upper and side surfaces of said control gate electrodes and side surfaces of said floating gate electrodes; an insulating interlayer formed on said field oxidation films and on said thermal oxidation film; contact hole passages extending through said insulating interlayer so as to expose a portion of each of said control gate electrodes; and a wire, formed on said insulating interlayer, for connecting said control gate electrodes to each other.

Claim 22

A device according to claim 17, wherein each floating gate electrode and each control gate electrode consists of polysilicon.

Claim 23

A device according to claim 17, wherein each floating gate electrode and each control gate electrode consist of polycide film.

Claim 24

A device according to claim 17, wherein each floating gate electrode and each control gate electrode consist of silicide film.

Claim 25

A device according to claim 17, wherein said wire consists of aluminum film.

Claim 26

A device according to claim 17, wherein said wire consists of tungsten film.

Claim 27

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of field oxidation films selectively formed on said semiconductor substrate to perform element isolation; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said plurality of field oxidation films; a plurality of memory cells each comprising a first gate insulating film, a floating gate electrode, a second insulating film, and a control gate electrode, formed by sequentially etching a first insulating film, a first polysilicon layer, a second insulating film, and a second polysilicon layer, which are sequentially formed on said semiconductor substrate and on said field oxidation films, so as to expose portions of said field oxidation films; a thermal oxidation film formed by thermally oxidizing upper and side surfaces of said control gate electrodes and side surfaces of said floating gate electrodes; a first insulating interlayer formed on said field oxidation films and on said thermal oxidation films; a plurality f first contact hole passages extending through said first insulating interlayer so as to expose portions of said control gate electrodes; a plurality of first wires, formed on said first insulating interlayer, for connecting said control gate electrodes to each other; a second insulating interlayer formed on said first insulating interlayer and on said plurality of first wires; a second contact hole passage extending through said second insulating interlayer so as to expose a portion of each of said plurality of first wires; and a second wire, formed on said second insulating interlayer so as to be in contact with said plurality of first wires through said second contact hole passage, for shunt-connecting said plurality of first wires.

Claim 28

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of field oxidation films selectively formed on said semiconductor substrate to perform element isolation; a first gate insulating film formed on an exposed surface of said semiconductor substrate and on said plurality of field oxidation films; a plurality of memory cells each comprising a first gate insulating film, a floating gate electrode, a second insulating film, and a control gate electrode, formed by sequentially etching a first insulating film, a first polysilicon layer, a second insulating film, and a second polysilicon layer, which are sequentially formed on said semiconductor substrate and on said field oxidation films, so as to expose portions of said field oxidation films; a thermal oxidation film formed by thermally oxidizing upper and side surfaces of said control gate electrodes and side surfaces of said floating gate electrodes; a first insulating interlayer formed on said field oxidation films and on said thermal oxidation films; a plurality f first contact hole passages extending through said first insulating interlayer so as to expose portions of said control gate electrodes; a plurality of first wires, formed on said first insulating interlayer, for connecting said control gate electrodes to each other; a second insulating interlayer formed on said first insulating interlayer and on said plurality of first wires; a second contact hole passage extending through said second insulating interlayer so as to expose a portion of each of said plurality of first wires; and a second wire, formed on said second insulating interlayer so as to be in contact with said plurality of first wires through said second contact hole passage, for shunt-connecting said plurality of first wires.

Claim 29

A device according to claim 23, wherein each floating gate electrode and each control gate electrode consists of polysilicon.

Claim 30

A device according to claim 23, wherein each floating gate electrode and each control gate electrode consists of polycide film

Claim 31

A device according to claim 23, wherein each floating gate electrode and each control gate electrode consists of silicide film.

Claim 32

A device according to claim 23, wherein said wires consist of aluminum film.

Claim 33

A device according to claim 23, wherein each wires consist of tungsten film.