US5150120A
Expired / Lapsed
US
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Multiplexed sigma-delta A/D converter
Assignee: Intersil Corp
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Filing: 1991-01-03
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Granted: 1992-09-22
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Expires: 2011-01-03
Abstract
Abstract A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.
Inventors
- 👤 Mohammad Yunus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:17
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/458; H03M3/466; H03M3/468; H03M3/47; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/436; H03M3/438; H03M3/454
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
112 words
A sigma-delta analog-to-digital converter comprising: a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal; signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall output digital signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and filtering means for filtering quantization noise from said overall digital output signal.
Claim 2
Dependent Claim
112 words
A sigma-delta analog-to-digital converter comprising: a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal; signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall output digital signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and filtering means for filtering quantization noise from said overall digital output signal.
Claim 3
Dependent Claim
30 words
A sigma-delta analog-to-digital converter according to claim 1, wherein said sigma-delta modulators are second-order modulators each containing two integrators in sequence and a comparator/latch circuit as an internal A/D converter.
Claim 4
Dependent Claim
16 words
A sigma-delta analog-to-digital converter according to claim 2, wherein said second-order modulators are switched-capacitor type modulators.
Claim 5
Dependent Claim
16 words
A sigma-delta analog-to-digital converter according to claim 2, wherein said second-order modulators have respective RC integrators.
Claim 6
Dependent Claim
39 words
A sigma-delta analog-to-digital converter according to claim 1, wherein said signal combining means is a multiplexor circuit having a plurality of phased multiplexor clocks applied thereto each corresponding to a respective one of the plurality N of sigma-delta modulators.
Claim 7
Dependent Claim
19 words
A sigma-delta analog-to-digital converter according to claim 1, wherein said modulator clocks are in phased sequence with each other.
Claim 8
Dependent Claim
21 words
A sigma-delta analog-to-digital converter according to claim 1 wherein said modulator clocks are equal to and in phase with each other.
Claim 9
Dependent Claim
18 words
A sigma-delta analog-to-digital converter according to claim 1, wherein said filtering means is a digital low pass filter.
Claim 10
Dependent Claim
31 words
A sigma-delta analog-to-digital converter according to claim 1, wherein said signal combining means is an adder for adding the modulator digital output signals together and providing said overall digital output signal.
Claim 11
Dependent Claim
23 words
A sigma-delta analog-to-digital converter according to claim 9, wherein said adder also serves as said filtering means by outputting a digital sum signal.
Claim 12
Dependent Claim
134 words
A sigma-delta analog-to-digital converter comprising: a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal, wherein said sigma-delta modulators are second-order modulators each containing two integrators in sequence and a comparator/latch circuit as an internal A/D converter; signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall digital output signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and filtering means for filtering quantization noise from said overall output digital signal.
Claim 13
Dependent Claim
134 words
A sigma-delta analog-to-digital converter comprising: a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal, wherein said sigma-delta modulators are second-order modulators each containing two integrators in sequence and a comparator/latch circuit as an internal A/D converter; signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall digital output signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and filtering means for filtering quantization noise from said overall output digital signal.
Claim 14
Dependent Claim
38 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said plurality N is four in number, and said overall digital output signal has an effective sampling rate that is four times the sampling frequency of the individual modulators.
Claim 15
Dependent Claim
16 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said second-order modulators are switched-capacitor type modulators.
Claim 16
Dependent Claim
16 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said second-order modulators have respective RC integrators.
Claim 17
Dependent Claim
39 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said signal combining means is a multiplexor circuit having a plurality of phased multiplexor clocks applied thereto each corresponding to a respective one of the plurality N of sigma-delta modulators.
Claim 18
Dependent Claim
19 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said modulator clocks are in phased sequence with each other.
Claim 19
Dependent Claim
21 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said modulator clocks are equal to and in phase with each other.
Claim 20
Dependent Claim
18 words
A sigma-delta analog-to-digital converter according to claim 11, wherein said filtering means is a digital low pass filter.
Claim 21
Dependent Claim
31 words
A sigma-delta analog-to-digital converter according to claim 17, wherein said signal combining means is an adder for adding the modulator digital output signals together and providing said overall digital output signal.
Claim 22
Dependent Claim
23 words
A sigma-delta analog to-digital converter according to claim 19, wherein said adder also serves as said filtering means by a digital sum signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-22 | 1996-03-23 | 1996-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-22 | 2000-03-23 | 2000-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-22 | 2004-03-23 | 2004-09-22 | $7700.00 | Window Closed / Lapsed |