Self-aligning ion-implantation method for semiconductor device having multi-gate type MOS transistor structure

Claim 1

A self-aligning ion-implantation method for semiconductor devices comprising a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged alternately and mutually insulatedly on channel regions located between drain regions and source regions of a semiconductor substrate so that said layers constitute a multigate type MOS transistor structure, comprising the steps of: forming said first gate electrode layers at uniform intervals on said channel regions in such a manner as to be electrically insulated from said substrate; ion-implanting an impurity having a conduction type different from that of said substrate into selected ones of said channel regions located between said first gate electrode layers; forming said second gate electrode layers on said channel regions located between said first gate electrode layers in such a manner as to be electrically insulated from said substrate and said first gate electrode layers, and in such a manner as for the peripheral portions of said second gate electrode layers to be overlapped with the peripheral portions of said first gate electrode layers, at least one of said second gate electrode layers being disposed above said selected channel regions doped with the impurity; and ion-implanting an impurity having a conduction type different from that of said substrate through said first gate electrode layers into selected others of said channel regions located below said first gate electrode layers, whereby the impurity is ion-implanted in a self-aligned manner due to adjacent ones of said second gate electrode layers.

Claim 9

A method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate, each said structure including a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged in an alternating sequence over a channel region between a drain and a source region and insulated from each other, comprising the steps of: forming said first gate electrode layers in spaced intervals on said channel region; ion-implanting an impurity into a first channel region located below the space between two of said first gate electrode layers; forming a second gate electrode layer in each space between two first gate electrode layers; each said second gate electrode layer overlaps a portion of the top surface of the two adjacent first gate electrode layers; conducting one of the following two steps, (1) forming a mask over two of said second gate electrode layers, and ion-implanting an impurity into a second channel region located below a first gate electrode layer between said two second gate electrode layers, using said mask, said ion implantation being through said first gate electrode layer above said second channel region; (2) ion-implanting an impurity into a second channel region located below one of said first gate electrode layers; forming a mask over said second gate electrode layer above said first channel region and said first gate electrode layer above said second channel region; ion-implanting a channel region between said first and second channel regions, using said mask, said ion implantation being through each gate electrode layer above said channel region between said first and second channel region; whereby the ion-implantation in said steps (1) and (2) is self-aligned and wherein: said first channel region is ion implanted with an impurity having a conduction type different from that of the substrate; in said step (1) said second channel region is ion implanted with an impurity having a conduction type different from that of the substrate; and in said step (2) said channel region between said first and second channel regions is ion implanted with an impurity having the same conduction type as that of the substrate.

Claim 10

A method for forming multi-gate MOS transistor structures within a semiconductor cell array on a substrate, each said structure including a plurality of first gate electrode layers and a plurality of second gate electrode layers arranged in an alternating sequence over a channel region between a drain and a source region and insulated from each other, comprising the steps of: forming said first gate electrode layers in spaced intervals on said channel region; ion-implanting an impurity into a first channel region located below the space between two of said first gate electrode layers; forming a second gate electrode layer in each space between two first gate electrode layers; each said second gate electrode layer overlaps a portion of the top surface of the two adjacent first gate electrode layers; conducting one of the following two steps, (1) forming a mask over two of said second gate electrode layers, and ion-implanting an impurity into a second channel region located below a first gate electrode layer between said two second gate electrode layers, using said mask, said ion implantation being through said first gate electrode layer above said second channel region; (2) ion-implanting an impurity into a second channel region located below one of said first gate electrode layers; forming a mask over said second gate electrode layer above said first channel region and said first gate electrode layer above said second channel region; ion-implanting a channel region between said first and second channel regions, using said mask, said ion implantation being through each gate electrode layer above said channel region between said first and second channel region; whereby the ion-implantation in said steps (1) and (2) is self-aligned and wherein: said first channel region is ion implanted with an impurity having a conduction type different from that of the substrate; in said step (1) said second channel region is ion implanted with an impurity having a conduction type different from that of the substrate; and in said step (2) said channel region between said first and second channel regions is ion implanted with an impurity having the same conduction type as that of the substrate.