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US5149663A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for manufacturing a Bi-CMOS semiconductor device

Assignee: Electronics and Telecommunications Research Institute
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Filing: 1991-10-21
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Granted: 1992-09-22
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Expires: 2011-10-21
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Abstract

Abstract There is provided a method of manufacturing Bi-CMOS semiconductor devices in which further comprises the steps of; depositing a polysilicon layer, an oxide film and a nitride film one and another in order to form the emitter and collector of a bipolar transistor, and the gates of a CMOS; forming an oxide film and a nitride film at the side wall of the polysilicon layer one and another; etching the exposed portions of an epitaxial layer and depositing other nitride film on the nitride film at the side wall; growing an oxide film on the etched portions of the epitaxial layer and removing all the nitride films; and implanting impurities on portions of the epitaxial layer exposed by the etched nitride films in order to make the inactive base region of the bipolar transistor and the source/drain regions of a PMOS transistor P+ type, and to make the source/drain regions of a NMOS transistor n+ type. Accordingly, the widths of the regions can be decreased and thus junction capacitance can be reduced in accordance with the magnitude of the decreased width.

Inventors

  • 👤 Sang H. Chai
  • 👤 Yong S. Koo
  • 👤 Kwang S. Kim
  • 👤 Kee S. Nam

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 09:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 380 words
A method for manufacturing a Bi-CMOS device comprising the steps of: (a) forming an N+ type huried layer upon a P type silicon substrate; (b) growing an N type epitaxial layer upon it; (c) depositing an oxide film and carrying out a masking process for defining a P well; (d) implanting and diffusing an impurity down to the N type epitaxial layer in order to form a P well; (e) removing the oxide film only on the P well and N type epitaxial layer; (f) growing an oxide, and depositing a nitride film on the oxide film upon the P well and N type epitaxial layer; (g) defining device active regions by means of an active region mask; (h) ion-implanting an impurity by means of a field mask in order to form P+ junction isolation regions; (i) growing an oxide film to form device isolation regions by means of an oxide isolation process; (j) growing a gate oxide film of CMOS transistor after removal of the oxide film and nitride film; (k) ion-implanting an impurity in order to form base and collector of bipolar transistor after removing the gate oxide film of the regions corresponding to the base and collector of the bipolar transistor; (l) forming N+ type polysilicon on the N type epitaxial layer corresponding to region in which the emitter of the bipolar transistor is formed and on the gate oxide film corresponding to regions in which gates of the CMOS transistor are formed, and sequentially depositing an oxide film and a first nitride film for defining the emitter and collector of the bipolar transistor and the gates of the CMOS transistor; (m) sequentially depositing an oxide film and a second nitride film at side walls of the N+ type polysilicon; (n) etching exposed portions of the N+epitaxial layer up to determined depth and depositing a third nitride film at side portions of the second nitride film; (o) depositing an oxide film on the etched portions of the epitaxial layer; and (p) implanting impurities to portions of the epitaxial layer exposed by removal of the second and third nitride film in order to make base region of the bipolar transistor and source/drain regions of a PMOS transistor P+type, and to make source/drain regions of an NMOS transistor N+type.
Claim 2
Independent Claim 380 words
A method for manufacturing a Bi-CMOS device comprising the steps of: (a) forming an N+ type huried layer upon a P type silicon substrate; (b) growing an N type epitaxial layer upon it; (c) depositing an oxide film and carrying out a masking process for defining a P well; (d) implanting and diffusing an impurity down to the N type epitaxial layer in order to form a P well; (e) removing the oxide film only on the P well and N type epitaxial layer; (f) growing an oxide, and depositing a nitride film on the oxide film upon the P well and N type epitaxial layer; (g) defining device active regions by means of an active region mask; (h) ion-implanting an impurity by means of a field mask in order to form P+ junction isolation regions; (i) growing an oxide film to form device isolation regions by means of an oxide isolation process; (j) growing a gate oxide film of CMOS transistor after removal of the oxide film and nitride film; (k) ion-implanting an impurity in order to form base and collector of bipolar transistor after removing the gate oxide film of the regions corresponding to the base and collector of the bipolar transistor; (l) forming N+ type polysilicon on the N type epitaxial layer corresponding to region in which the emitter of the bipolar transistor is formed and on the gate oxide film corresponding to regions in which gates of the CMOS transistor are formed, and sequentially depositing an oxide film and a first nitride film for defining the emitter and collector of the bipolar transistor and the gates of the CMOS transistor; (m) sequentially depositing an oxide film and a second nitride film at side walls of the N+ type polysilicon; (n) etching exposed portions of the N+epitaxial layer up to determined depth and depositing a third nitride film at side portions of the second nitride film; (o) depositing an oxide film on the etched portions of the epitaxial layer; and (p) implanting impurities to portions of the epitaxial layer exposed by removal of the second and third nitride film in order to make base region of the bipolar transistor and source/drain regions of a PMOS transistor P+type, and to make source/drain regions of an NMOS transistor N+type.

References Cited (Backward Citations)

US4816423A Cited
US5059546A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-09-22 1996-03-23 1996-09-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-09-22 2000-03-23 2000-09-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-09-22 2004-03-23 2004-09-22 $7700.00 Window Closed / Lapsed

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