Patent US5148500A successfully refreshed from Google Patents.
US5148500A
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Morphological processing system
Assignee: AOI INDUSTRIES Inc
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Filing: 1991-01-24
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Granted: 1992-09-15
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Expires: 2011-01-24
Abstract
Abstract Image processing elements forming an image processor for automatic inspection of circuits. Each processing element for performing a thinning algorithm passes along a data bit and a flag bit to each succeeding processing element. The flag bits permit a conditional deletion of a data bit. Within each processing element a feedback bit is used to indicate when a previous bit has been deleted. The skeletonized image is reviewed for identification of circuit geometries and counting the number of separate blobs. A report is generated in response to the identified geometry and blob count.
Inventors
- 👤 Richard P. Belanger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:47
CPC Classifications
G; G06; G06T; G06T5/00; G06T5/20; G06T5/30; G06V; G06V10/00; G06V10/20; G06V10/34
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
119 words
An image processing element comprising: means for receiving, in each of a series of time periods, a data bit and a flag bit, said data bit coming from a stream of data bits representative of a 2-dimensional image; logic means for generating a corrected data bit in response to at least said data bit and said flag bit; n parallel arrays of registers, where n is an integer; a plurality of line buffers connected with said n parallel arrays of registers such that said n parallel arrays hold a window of corrected data bits; and a lookup table for generating at least a data bit and a flag bit in response to at least said window of data bits.
Claim 2
Dependent Claim
119 words
An image processing element comprising: means for receiving, in each of a series of time periods, a data bit and a flag bit, said data bit coming from a stream of data bits representative of a 2-dimensional image; logic means for generating a corrected data bit in response to at least said data bit and said flag bit; n parallel arrays of registers, where n is an integer; a plurality of line buffers connected with said n parallel arrays of registers such that said n parallel arrays hold a window of corrected data bits; and a lookup table for generating at least a data bit and a flag bit in response to at least said window of data bits.
Claim 3
Dependent Claim
43 words
The image processing element of claim 1 wherein said lookup table may be programmed with a set of window templates for generating the data bit and the flag bit in response to a match between a template and said window of data bits.
Claim 4
Dependent Claim
23 words
The image processing element of claim 1 wherein aid logic means is further responsive to selected bits from said n arrays of registers.
Claim 5
Dependent Claim
34 words
The image processing element of claim 3 wherein said flag bit received by said receiving means has a state which causes said logic means to delete said data bit depending on said selected bits.
Claim 6
Dependent Claim
39 words
The image processing element of claim 1 wherein said lookup table further generates a new feedback bit and said lookup table is further responsive to an old feedback bit generated by said lookup table in the previous time period.
Claim 7
Dependent Claim
21 words
The image processing element of claim 5 wherein said feedback bit indicates whether said lookup table has performed a thinning operation.
Claim 8
Dependent Claim
156 words
An image processing element comprising: means for receiving over a series of consecutive time periods a stream of data bits representative of a 2-dimensional image, each data bit being received in one of said time periods; means for receiving flag bits from an adjacent image processing element; logic means for generating a corrected data bit in response at least to a data bit from said data bit receiving means and a flag bit from said flag bit receiving means; n parallel arrays of registers, where n is an integer; a plurality of line buffers connected with said n parallel arrays of registers such that said n parallel arrays hold a window of corrected data bits; and a lookup table for generating a data bit, a flag bit and a new feedback bit in response to said window of corrected data bits and an old feedback bit generated by said lookup table in the previous time period.
Claim 9
Dependent Claim
156 words
An image processing element comprising: means for receiving over a series of consecutive time periods a stream of data bits representative of a 2-dimensional image, each data bit being received in one of said time periods; means for receiving flag bits from an adjacent image processing element; logic means for generating a corrected data bit in response at least to a data bit from said data bit receiving means and a flag bit from said flag bit receiving means; n parallel arrays of registers, where n is an integer; a plurality of line buffers connected with said n parallel arrays of registers such that said n parallel arrays hold a window of corrected data bits; and a lookup table for generating a data bit, a flag bit and a new feedback bit in response to said window of corrected data bits and an old feedback bit generated by said lookup table in the previous time period.
Claim 10
Dependent Claim
30 words
The image processing element of claim 7 wherein said flag bit generated by said lookup table has a state which conditionally deletes the data bit generated by said lookup table.
Claim 11
Dependent Claim
23 words
The image processing element of claim 7 wherein said old feedback bit indicates whether a thinning operation occurred in the previous time period.
Claim 12
Dependent Claim
48 words
The image processing element of claim 7 wherein said lookup table may be programmed with a set of window templates for generating the data bit the flag bit and the new feedback bit in response to a match between a template and said window of corrected data bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-15 | 1996-03-16 | 1996-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-15 | 2000-03-16 | 2000-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-15 | 2004-03-16 | 2004-09-15 | $7700.00 | Window Closed / Lapsed |