Method for automatic optical inspection analysis of integrated circuits

Claim 1

An automatic method for optical inspection of integrated circuits, using an automatic inspection processor, comprising loading the processor with a design list of permissible distinctive feature positions, each permissible distinctive feature position including a feature type parameter and location parameter so as to identify the desired circuit in terms of a composite statement of features at appropriate locations, the method including the following steps: (a) taking a pixel image of the circuit layer section in terms of pixels at coordinate locations; (b) modifying selectively, by controlled skeletonization, the pixel image to emphasize features of the pixel image of the integrated circuit by thinning by a finite series of thinning steps resulting in skeletonization thin enough to contrast the pixel image by an amount for causing a circuit element of less than the minimum permitted circuit element width to disappear, and thinning enough to skeletonized original maximum width circuit elements, leaving features identifiable as T-joints, blob-joints and terminal ends at locations wherein the circuit element was appropriate in form to the feature type; (c) identifying emphasized features n the pixel image in terms of a position list of feature designations each including feature type parameter and feature location parameter further including detecting such T-joints, blob-joints and terminal ends as distinctive features from which violations may be inferred upon unfavorable comparison with the design list; (d) comparing the position list with the design list to infer violations and terminate upon occurrence of violation or proceed absent violation for pad verification; (e) thinning by an additional amount to provide total thinning sufficient to achieve the smallest residue blob-joint for a pad of minimum allowable area; (f) detecting T-joints, blob-joints, terminal ends and isolated pixel distinctive features, and (g) comparing the position list with the design list, includes detecting such T-joints, blob-joints, terminal ends and isolated pixel features as distinctive features from which pad violations may be inferred upon unfavorable comparison with the design list.