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US5148395A Expired / Lapsed US ⏱️ 0.0 years remaining

Dual eeprom cell with current mirror differential read

Assignee: Exar Corp
•
Filing: 1989-04-26
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Granted: 1992-09-15
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Expires: 2009-04-26
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Abstract

Abstract An EEPROM device having dual EEPROM transistor blocks for storing a charge and a current mirror for determining the difference in charge between the EEPROM transistor blocks. During a write operation, one EEPROM transistor block is charged while the other block is discharged. During a read operation, the current mirror attempts to supply equal current to each of the EEPROM transistor blocks. However, because each block has a different charge, more current will be forced through one leg of the current mirror. This results in a voltage difference across the legs of the current mirror which can be read by a voltage sensor.

Inventors

  • 👤 David K. Sowards

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 14:38
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C7/00; G11C7/14; G11C16/06; G11C16/26; G11C16/28

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 230 words
An EEPROM memory device comprising: a. a first EEPROM transistor block having at least one EEPROM transistor, said at least one transistor having a source, drain, and gate; b. a second EEPROM transistor block having at least one EEPROM transistor, said at least one transistor having a source, drain, and gate; c. a current mirror having a first leg coupled to the source of said at least one EEPROM transistor in the first EEPROM transistor block and a second leg coupled to the source of the EEPROM transistor in the second EEPROM transistor block; d. means, coupled to at least one of the legs of the current mirror, for detecting a voltage difference between the EEPROM transistor blocks; e. first switching means, coupled to the gate of each of the EEPROM transistors, for charging one of the EEPROM transistor blocks; f. second switching means, coupled to the drain of each of the EEPROM transistors, for discharging the other EEPROM transistor block not charged by said first switching means; g. means for disabling the current mirror; and h. first input means, coupled to the means for disabling the current mirror, for indicating when the current mirror should be disabled, wherein said first input means is also coupled to the first switching means for indicating when the first switching means should be activated to allow charging of a selected EEPROM transistor block.
Claim 2
Dependent Claim 230 words
An EEPROM memory device comprising: a. a first EEPROM transistor block having at least one EEPROM transistor, said at least one transistor having a source, drain, and gate; b. a second EEPROM transistor block having at least one EEPROM transistor, said at least one transistor having a source, drain, and gate; c. a current mirror having a first leg coupled to the source of said at least one EEPROM transistor in the first EEPROM transistor block and a second leg coupled to the source of the EEPROM transistor in the second EEPROM transistor block; d. means, coupled to at least one of the legs of the current mirror, for detecting a voltage difference between the EEPROM transistor blocks; e. first switching means, coupled to the gate of each of the EEPROM transistors, for charging one of the EEPROM transistor blocks; f. second switching means, coupled to the drain of each of the EEPROM transistors, for discharging the other EEPROM transistor block not charged by said first switching means; g. means for disabling the current mirror; and h. first input means, coupled to the means for disabling the current mirror, for indicating when the current mirror should be disabled, wherein said first input means is also coupled to the first switching means for indicating when the first switching means should be activated to allow charging of a selected EEPROM transistor block.
Claim 3
Dependent Claim 27 words
The EEPROM memory device of claim 1 further comprising second input means, coupled to the second switching means, for indicating the EEPROM transistor block to be discharged.

References Cited (Backward Citations)

US4271487A Cited
US4371956A Cited
US4725984A Cited
EP0224125A2 Cited
US4727519A Cited
US4791324A Cited
US4884241A Cited
US4933906A Cited
US4980859A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-09-15 1996-03-16 1996-09-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-09-15 2000-03-16 2000-09-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-09-15 2004-03-16 2004-09-15 $7700.00 Window Closed / Lapsed

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