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US5146570A
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System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution
Assignee: International Business Machines Corp
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Filing: 1990-07-03
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Granted: 1992-09-08
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Expires: 2010-07-03
Abstract
Abstract A method and apparatus are described for expanding the capability of an instruction prefetch buffer. The method and apparatus enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method and apparatus are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
Inventors
- 👤 Phillip D. Hester
- 👤 William M. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3836; G06F9/3842
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
121 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions in said processor having at last one branch-with-execute instruction, said method comprising: executing said branch-with-execute instruction resulting in a next successive instruction, a subject instruction, being next executed while a target instruction specified by the branch-with-execute instruction is being prefetched from the storage for execution after the execution of the subject instruction; storing the subject instruction in an instruction buffer; and determining an available location in the instruction buffer for holding the target instruction prior to execution of the target instruction and, clearing all other locations in said instruction buffer which are not storing the subject instruction.
Claim 2
Dependent Claim
121 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions in said processor having at last one branch-with-execute instruction, said method comprising: executing said branch-with-execute instruction resulting in a next successive instruction, a subject instruction, being next executed while a target instruction specified by the branch-with-execute instruction is being prefetched from the storage for execution after the execution of the subject instruction; storing the subject instruction in an instruction buffer; and determining an available location in the instruction buffer for holding the target instruction prior to execution of the target instruction and, clearing all other locations in said instruction buffer which are not storing the subject instruction.
Claim 3
Dependent Claim
45 words
A method according to claim 1 further including: executing said subject instruction; clearing the location in said instruction buffer in which said subject instruction was held prior to execution of the subject instruction; and, fetching said target instruction from said storage to said instruction buffer.
Claim 4
Dependent Claim
38 words
A method according to claim 2 further including a step of updating a pointer in said instruction buffer prior to fetching said target instruction, said updating step enabling target instruction decoding after said target instruction has been fetched.
Claim 5
Dependent Claim
29 words
A method according to claim 3 further including a step of allocating a location in said instruction buffer which is a value of said pointer for said target instruction.
Claim 6
Dependent Claim
19 words
A method according to claim 4 further including decoding a target instruction at said location in said instruction buffer.
Claim 7
Dependent Claim
148 words
In a data processing system including a processor and a storage from which said processor prefetches an instruction, an apparatus for executing a plurality of instructions in said processor having at least one branch-with-execute instruction, said apparatus comprising: means for executing said branch-with-execute instruction resulting in a next successive instruction, a subject instruction, being next executed while a target instruction specified by the branch-with-execute instruction is being prefetched from storage for execution after the execution of the subject instruction; means, connected to said executing means, for storing the subject instruction in an instruction buffer; means, connected to said executing and storing means, for determining an available location in the instruction buffer for holding a target instruction prior to execution of the target instruction; and means, connected to said executing, storing and determining means, for clearing all other locations in said instruction buffer which are not the subject instruction.
Claim 8
Dependent Claim
148 words
In a data processing system including a processor and a storage from which said processor prefetches an instruction, an apparatus for executing a plurality of instructions in said processor having at least one branch-with-execute instruction, said apparatus comprising: means for executing said branch-with-execute instruction resulting in a next successive instruction, a subject instruction, being next executed while a target instruction specified by the branch-with-execute instruction is being prefetched from storage for execution after the execution of the subject instruction; means, connected to said executing means, for storing the subject instruction in an instruction buffer; means, connected to said executing and storing means, for determining an available location in the instruction buffer for holding a target instruction prior to execution of the target instruction; and means, connected to said executing, storing and determining means, for clearing all other locations in said instruction buffer which are not the subject instruction.
Claim 9
Dependent Claim
71 words
An apparatus according to claim 6 further including means for executing said subject instruction, means connected to said subject instruction execution means for clearing the location in the instruction buffer in which the subject instruction was held prior to execution of the subject instruction; and means connected to said subject instruction executing means and said subject instruction clearing means, for fetching said target instruction from said storage to said instruction buffer.
Claim 10
Dependent Claim
46 words
An apparatus according to claim 7 further including means for updating a pointer in said instruction buffer prior to fetching the target instruction, wherein the means for updating the pointer includes means for enabling decoding of the target instruction after the target instruction has been fetched.
Claim 11
Dependent Claim
28 words
An apparatus according to claim 8 further including means for allocating a location in the instruction buffer which is a value of the pointer for the target instruction.
Claim 12
Dependent Claim
22 words
An apparatus according to claim 9 further including decoding means for decoding a target instruction at said location in said instruction buffer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-08 | 1996-03-09 | 1996-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-08 | 2000-03-09 | 2000-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-08 | 2004-03-09 | 2004-09-08 | $7700.00 | Window Closed / Lapsed |