Apparatus for processing bit streams

Claim 2

Apparatus for processing a stream of bits that have plural possible states and are received over an input line comprising a hardware comparator that compares first predetermined bits of said stream at predetermined positions in a group of bits in said stream, said predetermined bits being fewer in number than all bits in said group, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, said comparison input means being programmable to provide one of a plurality of different tables stored therein in response to a table select control signal an index generator that receives a comparison output from said comparator and generates an index based on the states of said predetermined bits indicated by said comparison output, and a processor for accessing said index and processing said group of said bits in said stream of bits in at least one of a plurality of different ways based on said index.

Claim 3

The apparatus of claim 1 further comprising data buffers connected to receive and store portions of said bit stream, said processor being connected to access said data buffers.

Claim 4

The apparatus of claim 2 further comprising descriptor storages associated with respective said data buffers for storing descriptor entries relating to data stored in said data buffers.

Claim 5

The apparatus of claim 3 wherein a said descriptor storage is connected to receive and store said index.

Claim 6

The apparatus of claim 1 wherein said comparator is programmable to respond to a field select control signal so that the predetermined bits compared are a function of said field select control signal.

Claim 7

The apparatus of claim 5 wherein said field select control signal comprises a start location signal indicating the start bit of the field to be used for the compare, and a length signal indicating the length of the bit field to be used for the compare.

Claim 8

The apparatus of claim 5 wherein said processor comprises means for providing said field select control signal.

Claim 9

The apparatus of claim 1 wherein said comparison input means is programmable to provide a different said table in response to a value generated as the result of an initial comparison of predetermined bits of said stream of bits.

Claim 10

The apparatus of claim 1 wherein said comparison input means comprises a table memory in which tables of comparison values are stored.

Claim 11

The apparatus of claim 9 further comprising a separate memory in which table entries are stored, and wherein said table memory also stores a control entry identifying a table entry in said separate memory including a table of comparison values to be stored in said table memory.

Claim 12

The apparatus of claim 9 wherein an entry identifying the predetermined bits to be compared is also stored in said table memory.

Claim 13

The apparatus of claim 9 wherein an entry indicating whether said group of bits should be discarded based upon the results of said compare is also stored in said table memory.

Claim 14

The apparatus of claim 9 wherein an entry indicating whether an interrupt should be generated based upon the results of said compare is also stored in said table memory.

Claim 15

The apparatus of claim 9 wherein an entry identifying a further table of comparison values is also stored in said table memory.

Claim 16

The apparatus of claim 9 wherein an entry identifying whether an index should replace said predetermined bits in said bit stream is stored in said table memory.

Claim 17

The apparatus of claim 9 wherein an entry identifying where the group of bits should be routed is stored in said table memory.

Claim 18

The apparatus of claim 10 wherein said control entry also identifies the predetermined bits to be compared.

Claim 19

The apparatus of claim 10 wherein said table entry also identifies a further control entry to be stored in said table memory, said further control entry identifying a further table entry including comparison values to be stored in said table memory.

Claim 20

The apparatus of claim 9 wherein said comparison input means also comprises a memory state machine for loading table entries containing comparison values in said table memory and for providing said comparison values in said table memory to said comparator.

Claim 21

The apparatus of claim 10, 17, or 18 wherein said comparison input means also comprises a memory state machine for loading said entries in said table memory, for providing comparison values in said table memory to said comparator, and for deleting said entries after comparisons have been made and loading further entries in said table memory.

Claim 22

The apparatus of claim 19 wherein said index generator comprises a chip control state machine that generates said index and controls operation of said comparator.

Claim 23

The apparatus of claim 1 wherein said predetermined bits comprises a destination address of an intended recipient of said group of bits, said index identifies an intended recipient, and said processor comprises means responsive to said index for transmitting said group of bits to said intended recipient.

Claim 24

The apparatus of claim 1 wherein predetermined bits identify a protocol, said index identifies a protocol, and said processor comprises means responsive to said index for processing said group of bits according to said protocol.

Claim 25

The apparatus of claim 1 wherein said predetermined bits identify a data compression algorithm, said index identifies a data compression algorithm, and said processor comprises means responsive to said index for expanding said group of bits according to said algorithm.

Claim 26

The apparatus of claim 1 wherein said hardware comparator compares second predetermined bits of said stream that indicate a special message related to management of said processor, and wherein said processor comprises means for acting on said special message in response to it.

Claim 27

The apparatus of claim 1 wherein said processor comprises a bridge having at least one port to a different network, said index identifies a said port, and said processing includes transmitting said group of bits to said port.

Claim 28

The apparatus of claim 26 wherein said processor comprises means for translating fields of said group in one network's protocol into another network's protocol.

Claim 29

The apparatus of claim 1 further comprising ring buffers for temporarily storing bits of said bit stream while said index is being generated.

Claim 30

The apparatus of claim 1 further comprising means to provide an interrupt signal to said processing means upon completion of comparing said predetermined bits.

Claim 31

The apparatus of claim 1 wherein said apparatus comprises a node of a local area network.

Claim 32

The apparatus of claim 1 wherein said stream of bits comprises Ethernet frames.

Claim 33

The apparatus of claim 1 wherein said stream of bits comprises Ethernet frames and IEEE 802.3 frames, and said index identifies whether said group of bits is an Ethernet frame or an IEEE 802.3 frame.

Claim 34

Apparatus for processing source data bits for transmitting over an output line, said bits having plural possible states, said apparatus comprising a hardware comparator that compares predetermined bits at predetermined positions in a group of bits of said source data bits, said predetermined bits being fewer in number than all bits in a said group, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, said comparison input means being programmable to provide one of a plurality of different tables stored therein in response to a table select control signal, an index generator that receives a comparison output from said hardware comparator and generates an index based on the states of said predetermined bits indicated by said comparison output, and a processor for accessing said index and modifying said group of said source data bits in one of a plurality of different ways prior to converting said source data bits to a stream of bits to be transmitted.

Claim 35

Apparatus for processing source data bits for transmitting over an output line, said bits having plural possible states, said apparatus comprising a hardware comparator that compares predetermined bits at predetermined positions in a group of bits of said source data bits, said predetermined bits being fewer in number than all bits in a said group, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, said comparison input means being programmable to provide one of a plurality of different tables stored therein in response to a table select control signal, an index generator that receives a comparison output from said hardware comparator and generates an index based on the states of said predetermined bits indicated by said comparison output, and a processor for accessing said index and modifying said group of said source data bits in one of a plurality of different ways prior to converting said source data bits to a stream of bits to be transmitted.

Claim 36

The apparatus of claim 33 wherein said index identifies transmit data to be placed in a frame to be transmitted.

Claim 37

The apparatus of claim 34 wherein said transmit data is placed in said frame at a field prescribed by a start location signal and a field select aperture signal.

Claim 38

A circuit for filtering a stream of bits that have plural possible states and are received over an input line comprising a hardware comparator that compares first predetermined bits of said stream at predetermined locations in a group of bits in said stream, said predetermined bits being fewer in number than all bits in said group, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, said comparison input means being programmable to provide one of a plurality of different tables stored therein in response to a table select control signal, and an index generator that receives a comparison output from said comparison input means and generates an index based on the states of said predetermined bits indicated by said comparison output, said index indicating one of a plurality of different ways that said group of said bits in said stream of bits is to be processed by an external processor.

Claim 39

A circuit for filtering a stream of bits that have plural possible states and are received over an input line comprising a hardware comparator that compares first predetermined bits of said stream at predetermined locations in a group of bits in said stream, said predetermined bits being fewer in number than all bits in said group, comparison input means to provide a table of comparison values to said hardware comparator for comparison with said predetermined bits of said stream, said comparison input means being programmable to provide one of a plurality of different tables stored therein in response to a table select control signal, and an index generator that receives a comparison output from said comparison input means and generates an index based on the states of said predetermined bits indicated by said comparison output, said index indicating one of a plurality of different ways that said group of said bits in said stream of bits is to be processed by an external processor.

Claim 40

The apparatus of claim 36 wherein said comparator is programmable to respond to a field select control signal so that the predetermined bits compared are a function of said field select control signal.

Claim 41

The circuit of claim 36 wherein said comparison input means comprises a table memory in which table entries including said comparison values are stored.

Claim 42

The apparatus of claim 38 further comprising a separate memory in which table entries are stored, and wherein said table memory also stores a control entry identifying a table entry in said separate memory including a table of comparison values to be stored in said table memory.

Claim 43

The apparatus of claim 38 wherein said comparison input means also comprises a memory state machine for loading said entries in said table memory and for providing comparison values in said table memory to said comparators.

Claim 44

The circuit of claim 38 or 39 wherein said comparison input means also comprises a memory state machine for loading said entries in said table memory, for providing comparison values in said table memory to said comparators, and for deleting said entries and loading further entries in said table memory after comparisons have been made.