Method for forming data block protection information for serial data bit sequences by means of cyclical binary codes

Claim 1

A method for data protection in the transmission of data blocks having serial data bit sequences, comprising the steps of: forming data block protection information code words by use of cyclical binary codes in a coder unit at the transmission side, forming corresponding code words with a coder unit at the reception side, providing each of said coders with registers representing the members of a binary code polynomial, and with binary logic elements arranged in relation to said registers so that a binary block protection information code word is produced by means of a binary arithmetic operation, employing the binary code polynomial defined by the data bit sequence of a data block as an operand in said arithmetic operation, and said binary block protection information code word defined as a result of said arithmetic operation, serially attaching said code word to the data block at the transmission side, comparing the transmitted code word with a code word generated at the receiving side, to derive an error detection signal, said registers (R) in said register chains (RK) being allocated, cyclically, from lowest to highest order in ascending sequence of the polynomial ordinal numbers of said binary code polynomial, said registers (R) being arranged following one another in a plurality of K register chains with K corresponding to the ration of the bit clock repetition rate (DT) of the data bit sequence (D) to the reduced processing clock repetition rate (VT) of the coder unit, with each such chain having a highest order register, converting the serial data bit sequence (D) to parallel form by parallel converter means receiving said bit sequence at the data clock rate (DT) and providing parallel bit sequences at said reduced clock rate (VT), forming a plurality of operation information signals in response to said converter means and the outputs of said highest order registers in said chains, and supplying said operation information signals to said logic elements which follow registers representing specific terms in the binary code polynomial, whereby the block protection information code word is formed by binary arithmetic operations in response to said data list and the outputs of said highest order registers at the rate of the processing clock (VT), and dependent on the connections of said operation information signals to said registers.

Claim 2

A method for data protection in the transmission of data blocks having serial data bit sequences, comprising the steps of: forming data block protection information code words by use of cyclical binary codes in a coder unit at the transmission side, forming corresponding code words with a coder unit at the reception side, providing each of said coders with registers representing the members of a binary code polynomial, and with binary logic elements arranged in relation to said registers so that a binary block protection information code word is produced by means of a binary arithmetic operation, employing the binary code polynomial defined by the data bit sequence of a data block as an operand in said arithmetic operation, and said binary block protection information code word defined as a result of said arithmetic operation, serially attaching said code word to the data block at the transmission side, comparing the transmitted code word with a code word generated at the receiving side, to derive an error detection signal, said registers (R) in said register chains (RK) being allocated, cyclically, from lowest to highest order in ascending sequence of the polynomial ordinal numbers of said binary code polynomial, said registers (R) being arranged following one another in a plurality of K register chains with K corresponding to the ration of the bit clock repetition rate (DT) of the data bit sequence (D) to the reduced processing clock repetition rate (VT) of the coder unit, with each such chain having a highest order register, converting the serial data bit sequence (D) to parallel form by parallel converter means receiving said bit sequence at the data clock rate (DT) and providing parallel bit sequences at said reduced clock rate (VT), forming a plurality of operation information signals in response to said converter means and the outputs of said highest order registers in said chains, and supplying said operation information signals to said logic elements which follow registers representing specific terms in the binary code polynomial, whereby the block protection information code word is formed by binary arithmetic operations in response to said data list and the outputs of said highest order registers at the rate of the processing clock (VT), and dependent on the connections of said operation information signals to said registers.

Claim 4

The method according to claims 1 or 2, including the step of allocating the polynomial ordinal numbers to the individual registers of each chin in the sequence N, N+K, N+2K . . . +N+(G/K-1)K, in which N is an integer from 1 to K corresponding to an individual register chain.

Claim 5

The method according to claims 3, including the step that, in the case of the 2 through K missing binary code polynomial members between two registers (R) of a register chain, at the locations defined by the plurality mth of the first and of the missing members between the preceding register (R) of the register chain and the appearance of the term, dividing the mth bit of the 1 through K possible data bits by the output information of the mth bit of the register chains, and using the outputs produced thereby for forming operation information signals representing the position of terms of said polynomial and in the case of more than two terms at and between the first and second 2 through K missing binary code polynomial members, the operation information signals are binarily divided in accordance with the sequence of their presence, and dividing the result by a further correspondingly formed operation information, in the case of the presence of further terms in succession in accordance with the sequence of their presence, and operating the respective logic elements with corresponding outputs of said means for forming the operation information signals (EBV).

Claim 6

The method according to any of claims 4, including the steps of reading out the division remainder from the register chains (RK1 and RK2), in the coder unit at the transmission side, multiplexing the register chains (RK1 and RK2) in synchronism with the data bit clock (DT) of the data bit sequence (D), and attaching the serial block protection information code word (BSI) to the end of the data block information by multiplexing (MUX2).

Claim 7

The method according to any of claims 5, including the steps of comparing the data block protection information code word formed at the transmitter side with the data block protection information code word formed at the receiver side to produce a signal corresponding to the quality of said transmission indicating an error-free data bit sequence transmission or a data bit sequence transmission having a single error, or a data bit sequence transmission having a multiple error.

Claim 8

The method of any of claims 6, including the steps of binarily dividing the data block protection information code word (BSI) formed at the reception side and stored in the register chains (RK1 and RK2) by the data block protection information code word formed at the transmission side of the transmission, and inspecting the division remainder present at the register outputs, whereby when all of said outputs represent the binary "0", a signal indicating error-free data bit sequence transmission is generated, and, in the case of the different binary information at the register outputs, a signal indicating a faulty data bit sequence transmission is formed.

Claim 9

The method according to any of claims 7, including the step of employing exclusive-Or gates for said binary division elements.