Circuit for checking bit errors in a received BCH code succession by the use of primitive and non-primitive polynomials

Claim 1

An error checking circuit responsive to an input succession of bit sequences for checking bit errors in said input succession by deciding whether each bit sequence includes a single error or a t-tuple error where t represents an integer which is greater than unity, said single error being present at a bit location in said each bit sequence, each of said bit sequences being determined by a combination of a predetermined number of information bits and a preselected number of check bits generated by a predetermined generator polynomial'to ensure a minimum intercode distance which is not less than four, said predetermined generator polynomial being equal to a product of factors comprising a primitive and a non-primitive polynomial, said error checking circuit comprising: first dividing means for successively dividing the individual bit sequences by said primitive polynomial to calculate first residues, respectively, and to produce first residue signals representative of the respective first residues, the first residues calculated when the single errors are present in the bit sequences divided by said primitive polynomial, respectively, becoming first non-zero residues, respectively, said first non-zero residues being unique with respect to the bit locations at which the last-mentioned single errors are present, respectively; second dividing means for successively dividing the individual bit sequences by said non-primitive polynomial to calculate second residues, respectively, and to produce second residue signals representative of the respective second residues, the second residues calculated in whichever of a first case where the bit sequences divided by said non-primitive polynomial include the single errors, respectively, and a second case where the bit sequences divided by said non-primitive polynomial include the t-tuple errors, respectively, becoming second special residues, respectively; memorizing means for memorizing a plurality of reference signals representative of reference numbers, respectively, said reference numbers being in one-to-one correspondence to said first non-zero residues and being identical with those of said second special residues which would be calculated by said second dividing means only in said first case; accessing means responsive to said first residue signals for accessing said memorizing means to make said memorizing means produce said reference signals as output reference signals, respectively, when the first residue signals responsive to which said memorizing means is accessed represent said first non-zero residues, respectively, the output reference signal produced when the first residue signal responsive to which said memorizing means is accessed represents one of said first non-zero residues being representative of the reference number which is in one-to-one correspondence to said one of the first non-zero residues; comparing means for comparing the second residue signal produced when each bit sequence is divided by said non-primitive polynomial with the output reference signal produced in response to the first residue signal produced when the last-mentioned bit sequence is divided by said primitive polynomial, said comparing means thereby producing a result signal representative of presence of a single and a t-tuple error in the last-mentioned bit sequence when the reference number represented by the last-mentioned output reference signal is in one-to-one correspondence to the first non-zero residue represented by the last-mentioned first residue signal and is not, respectively.