Subscriber unit for wireless digital subscriber communication system

Claim 2

An FIR chip for use in a subscriber unit for a wireless digital telephone system wherein the subscriber unit includes a processing means for transcoding an input signal to provide digital input symbols, for demodulating an output signal received from a second unit within the system and for synthesizing digital output symbols from the demodulated output signal, means responsive to the processing means for providing filtered digital input symbols, means for modulating an intermediate frequency signal with the filtered input symbols, and means for transmitting the modulated intermediate frequency signal to the second unit and for receiving an output signal from the second unit, the FIR chip comprising: means for internal address decoding to allow the processing means to access internal functions of the FIR chip; a control and status register which allows the processing means to read the status of and control internal functions of the FIR chip; means for FIR filtering to filter the digital input symbols; means for control timing which allows the processing means to control the FIR filtering means; and means for generating timing signals for timing transcoding operations and synthesizing operations connected to the processing means.

Claim 3

The FIR chip of claim 1 further including a ringer control means operatively associated with the control and status registers, said ringer control means permitting the processing means to control a ringer circuit of the subscriber unit.

Claim 4

The FIR chip of claim 2 further including a watchdog timer circuit operatively associated with the control and status register for resetting said processing means.

Claim 5

The FIR chip of claim 1 further including a sample buffer for operative association with the processing means for buffering receive data samples before the data samples are output to the processing means.

Claim 6

The FIR chip of claim 1 further including a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to the timing signals generating means.

Claim 7

The FIR chip of claim 1 further including an external address decoding means for operative association with the processing means to permit the processing means to access the remaining components of the subscriber unit.

Claim 8

In a subscriber unit for a wireless digital telephone system wherein the subscriber unit includes a processing means for transcoding an input signal to provide digital input symbols, for demodulating an output signal received from a second unit within the system, and for synthesizing digital output symbols from the demodulated output signal, means responsive to the processing means for providing filtered digital input symbols, means for modulating an intermediate frequency signal with the filtered input symbols, means for transmitting the modulated intermediate frequency signal to the second unit and for receiving an output signal from the second unit, the improvement comprising an FIR chip which includes: means for internal address decoding connected to the processing means, to allow the processing means to access the internal functions of the FIR chip; means for FIR filtering, connected to the processing means, to filter the digital input symbols; means for control timing which allows the processing means to control the FIR filtering means; means for generating timing signals for timing transcoding operations and synthesizing operations in the processing means; a control and status register, connected to the processing means, which allows the processing means to read the status of and control the internal functions of the integrated circuit; a ringer control means connected to the control and status registers, said ringer control means allows the processing means to control a ringer circuit of the subscriber unit; a watchdog timer circuit, connected to the control and status register, for resetting said processing means; a sample buffer for buffering received data samples before the data samples are output to the processing means; a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to the timing means; an external address decoding means, connected to the processing means, which allows the processing means to access the remaining components of the subscriber unit.

Claim 9

In a subscriber unit for a wireless digital telephone system wherein the subscriber unit includes a processing means for transcoding an input signal to provide digital input symbols, for demodulating an output signal received from a second unit within the system, and for synthesizing digital output symbols from the demodulated output signal, means responsive to the processing means for providing filtered digital input symbols, means for modulating an intermediate frequency signal with the filtered input symbols, means for transmitting the modulated intermediate frequency signal to the second unit and for receiving an output signal from the second unit, the improvement comprising an FIR chip which includes: means for internal address decoding connected to the processing means, to allow the processing means to access the internal functions of the FIR chip; means for FIR filtering, connected to the processing means, to filter the digital input symbols; means for control timing which allows the processing means to control the FIR filtering means; means for generating timing signals for timing transcoding operations and synthesizing operations in the processing means; a control and status register, connected to the processing means, which allows the processing means to read the status of and control the internal functions of the integrated circuit; a ringer control means connected to the control and status registers, said ringer control means allows the processing means to control a ringer circuit of the subscriber unit; a watchdog timer circuit, connected to the control and status register, for resetting said processing means; a sample buffer for buffering received data samples before the data samples are output to the processing means; a fanout buffer for receiving a master clock signal from the subscriber unit for buffering the master clock signal before being input to the timing means; an external address decoding means, connected to the processing means, which allows the processing means to access the remaining components of the subscriber unit.

Claim 10

The improved subscriber unit of claim 7 wherein the FIR chip further includes an internal address bus which allows communication between the control and status registers, sample buffer, the internal address decoding means, the timing means, the ringer control means, and the watchdog timer circuit.