Patent US5141887A successfully refreshed from Google Patents.
US5141887A
Expired / Lapsed
US
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Low voltage, deep junction device and method
Assignee: Semiconductor Components Industries LLC
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Filing: 1991-04-17
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Granted: 1992-08-25
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Expires: 2011-04-17
Abstract
Abstract A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0×10 16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.
Inventors
- 👤 Hang M. Liaw
- 👤 Frank S. d'Aragona
- 👤 Raymond M. Roop
- 👤 Dennis R. Olsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:57
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/10; H10P70/12; H10P10/00; H10P10/12; H10P10/128; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
105 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first silicon wafer of a first conductivity type, said first wafer having a first surface, a second surface and a dopant Concentration of at least 4.0×10 16 atoms/cc; providing a second silicon wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; removing impurities from said first and second wafers; and bonding said first silicon surfaces of said first and second wafers directly together.
Claim 2
Independent Claim
105 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first silicon wafer of a first conductivity type, said first wafer having a first surface, a second surface and a dopant Concentration of at least 4.0×10 16 atoms/cc; providing a second silicon wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; removing impurities from said first and second wafers; and bonding said first silicon surfaces of said first and second wafers directly together.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein the first and second wafers have the same concentration and diffusion coefficient of dopants and the dopant concentration is at least 1.5×10 17 atoms/cc.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein the first and second wafers have different dopant concentrations.
Claim 5
Dependent Claim
39 words
The method of claim 1 wherein dopant of the opposite conductivity type of one of the first and second wafers is diffused into the first surface of one of said first and second wafers prior to the bonding step.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein an epitaxial layer is formed on the first surface of one or both of the first and second wafers prior to the bonding step.
Claim 7
Dependent Claim
10 words
The method of claim 5 wherein multiple junctions are formed.
Claim 8
Dependent Claim
30 words
The method of claim 1 wherein an additional doped wafer is bonded to the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 9
Dependent Claim
29 words
The method of claim 1 wherein an epitaxial layer is formed on the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 10
Dependent Claim
46 words
The method of claim 1 wherein the removing impurities step includes growing sacrificial thermal oxide on the first and second wafers, said oxide being grown at a temperature in the range of 900 to 1200 degrees centigrade and causing gettering of said first and second wafers.
Claim 11
Dependent Claim
29 words
The method of claim 9 wherein the first and second wafers are subjected to trichloroethane during or after oxide growth to vaporize heavy metal impurities from the surfaces thereof.
Claim 12
Independent Claim
119 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing first and second silicon wafers of opposite conductivity types, each having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; cleaning said first and second surfaces of said first and second surfaces with at least one of the group consisting of acidic and basic solutions; gettering said first and second wafers by growing sacrificial thermal oxide thereon at a temperature in the range of 900 to 1200 degrees centigrade; removing said sacrificial thermal oxide; and bonding said first silicon surfaces of said first and second wafers directly together.
Claim 13
Independent Claim
119 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing first and second silicon wafers of opposite conductivity types, each having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; cleaning said first and second surfaces of said first and second surfaces with at least one of the group consisting of acidic and basic solutions; gettering said first and second wafers by growing sacrificial thermal oxide thereon at a temperature in the range of 900 to 1200 degrees centigrade; removing said sacrificial thermal oxide; and bonding said first silicon surfaces of said first and second wafers directly together.
Claim 14
Dependent Claim
30 words
The method of claim 11 wherein the first and second wafers have the same concentration and diffusion coefficient of dopants and the dopant concentration is at least 1.5×10 17 atoms/cc.
Claim 15
Dependent Claim
15 words
The method of claim 11 wherein the first and second wafers have different dopant concentrations.
Claim 16
Dependent Claim
39 words
The method of claim 11 wherein dopant of the opposite conductivity type of one of the first and second wafers is diffused into the first surface of one of said first and second wafers prior to the bonding step.
Claim 17
Dependent Claim
30 words
The method of claim 11 wherein an epitaxial layer is formed on the first surface of one or both of the first and second wafers prior to the bonding step.
Claim 18
Dependent Claim
10 words
The method of claim 15 wherein multiple junctions are formed.
Claim 19
Dependent Claim
30 words
The method of claim 11 wherein an additional doped wafer is bonded to the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 20
Dependent Claim
29 words
The method of claim 11 wherein an epitaxial layer is formed on the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 21
Dependent Claim
29 words
The method of claim 11 wherein the first and second wafers are subjected to trichloroethane during or after oxide growth to vaporize heavy metal impurities from the surfaces thereof.
Claim 22
Independent Claim
130 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first silicon wafer of a first conductivity type, said first wafer having a first surface, a second a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; providing a second silicon wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; forming an epitaxial silicon layer on the first surface of one or both of said first and second wafers; removing impurities from said first and second wafers; and bonding said first silicon surfaces including said epitaxial layer of said first and second wafers directly together.
Claim 23
Independent Claim
130 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first silicon wafer of a first conductivity type, said first wafer having a first surface, a second a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; providing a second silicon wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; forming an epitaxial silicon layer on the first surface of one or both of said first and second wafers; removing impurities from said first and second wafers; and bonding said first silicon surfaces including said epitaxial layer of said first and second wafers directly together.
Claim 24
Dependent Claim
30 words
The method of claim 20 wherein the first and second wafers have the same concentration and diffusion coefficient of dopants and the dopant concentration is at least 1.5×10 17 atoms/cc.
Claim 25
Dependent Claim
15 words
The method of claim 20 wherein the first and second wafers have different dopant concentrations.
Claim 26
Dependent Claim
39 words
The method of claim 20 wherein dopant of the opposite conductivity type of one of the first and second wafers is diffused into the first surface of one of said first and second wafers prior to the bonding step.
Claim 27
Dependent Claim
10 words
The method of claim 20 wherein multiple junctions are formed.
Claim 28
Dependent Claim
30 words
The method of claim 20 wherein an additional doped wafer is bonded to the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 29
Dependent Claim
29 words
The method of claim 20 wherein an epitaxial layer is formed on the second surface of one or both of the first and second wafers to create multiple junctions.
Claim 30
Dependent Claim
46 words
The method of claim 20 wherein the removing impurities step includes growing sacrificial thermal oxide on the first and second wafers, said oxide being grown at a temperature in the range of 900 to 1200 degrees centigrade and causing gettering of said first and second wafers.
Claim 31
Dependent Claim
29 words
The method of claim 27 wherein the first and second wafers are subjected to trichloroethane during or after oxide growth to vaporize heavy metal impurities from the surfaces thereof.
Claim 32
Independent Claim
134 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first semiconductor wafer of a first conductivity type, said first wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; providing a second semiconductor wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration at least 4.0×10 16 atoms/cc; removing impurities from said first and second wafers; bonding said first semiconductor surfaces of said first and second wafers directly together; and bonding an additional doped semiconductor wafer or forming a semiconductor epitaxial layer on the second surface of one or both of said first and second wafers to crete multiple junctions.
Claim 33
Independent Claim
134 words
A method of fabricating a deep junction device having a breakdown voltage of less than 20 volts, said method comprising the steps of: providing a first semiconductor wafer of a first conductivity type, said first wafer having a first surface, a second surface and a dopant concentration of at least 4.0×10 16 atoms/cc; providing a second semiconductor wafer of a second conductivity type, said second wafer having a first surface, a second surface and a dopant concentration at least 4.0×10 16 atoms/cc; removing impurities from said first and second wafers; bonding said first semiconductor surfaces of said first and second wafers directly together; and bonding an additional doped semiconductor wafer or forming a semiconductor epitaxial layer on the second surface of one or both of said first and second wafers to crete multiple junctions.
Claim 34
Dependent Claim
30 words
The method of claim 29 wherein the first and second wafers have the same concentration and diffusion coefficient of dopants and the dopant concentration is at least 1.5×10 17 atoms/cc.
Claim 35
Dependent Claim
15 words
The method of claim 29 wherein the first and second wafers have different dopant concentrations.
Claim 36
Dependent Claim
39 words
The method of claim 29 wherein dopant of the opposite conductivity type of one of the first and second wafers is diffused into the first surface of one of said first and second wafers prior to the bonding step.
Claim 37
Dependent Claim
30 words
The method of claim 29 wherein an epitaxial layer is formed on the first surface of one or both of the first and second wafers prior to the bonding step.
Claim 38
Dependent Claim
10 words
The method of claim 33 wherein multiple junctions are formed.
Claim 39
Dependent Claim
46 words
The method of claim 29 wherein the removing impurities step includes growing sacrificial thermal oxide on the first and second wafers, said oxide being grown at a temperature in the range of 900 to 1200 degrees centigrade and causing gettering of said first and second wafers.
Claim 40
Dependent Claim
29 words
The method of claim 29 wherein the first and second wafers are subjected to trichloroethane during or after oxide growth to vaporize heavy metal impurities from the surfaces thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |