Patent US5141879A successfully refreshed from Google Patents.
US5141879A
Expired / Lapsed
US
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Method of fabricating a FET having a high trap concentration interface layer
Assignee: Individual
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Filing: 1990-08-06
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Granted: 1992-08-25
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Expires: 2010-08-06
Abstract
Abstract A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.
Inventors
- 👤 Herbert Goronkin
- 👤 Saied N. Tehrani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:10
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/50; H10D62/53; Y; Y10; Y10S; Y10S438/00; Y10S438/904
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
63 words
A method of fabricating a MESFET having a high trap concentration layer comprising the steps of: providing a semi-insulating substrate; forming a high trap concentration layer in said substrate; forming a non-intentionally doped buffer layer on said high trap concentration layer; forming a conductive layer on said buffer layer; and forming a source, a Schottky gate and a drain on the FET layers.
Claim 2
Independent Claim
63 words
A method of fabricating a MESFET having a high trap concentration layer comprising the steps of: providing a semi-insulating substrate; forming a high trap concentration layer in said substrate; forming a non-intentionally doped buffer layer on said high trap concentration layer; forming a conductive layer on said buffer layer; and forming a source, a Schottky gate and a drain on the FET layers.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the substrate comprises a III-V compound semiconductor.
Claim 4
Dependent Claim
19 words
The method of claim 2 wherein the high trap concentration layer and the buffer layer comprise the same material.
Claim 5
Dependent Claim
18 words
The method of claim 3 wherein the high trap concentration layer and the buffer layer comprise gallium arsenide.
Claim 6
Dependent Claim
18 words
The method of claim 1 wherein the implanting of oxygen is done in either blanket or selective form.
Claim 7
Independent Claim
77 words
A method of fabricating a MESFET having a high trap concentration interface layer comprising the steps of: providing a III-V compound semi-insulating substrate. forming a high trap concentration interface layer in said substrate by implanting oxygen therein; forming an non-intentionally doped gallium arsenide buffer layer on said high trap concentration interface layer; forming a doped aluminum gallium arsenide layer on said buffer layer; and forming a source, a Schottky gate and a drain on the FET layers.
Claim 8
Independent Claim
77 words
A method of fabricating a MESFET having a high trap concentration interface layer comprising the steps of: providing a III-V compound semi-insulating substrate. forming a high trap concentration interface layer in said substrate by implanting oxygen therein; forming an non-intentionally doped gallium arsenide buffer layer on said high trap concentration interface layer; forming a doped aluminum gallium arsenide layer on said buffer layer; and forming a source, a Schottky gate and a drain on the FET layers.
Claim 9
Dependent Claim
19 words
The method of claim 6 wherein the high trap concentration layer comprises the same material as the buffer layer.
Claim 10
Dependent Claim
18 words
The method of claim 6 wherein the implanting of oxygen is done in either blanket or selective form.
Claim 11
Independent Claim
82 words
A method of fabricating a MESFET having a high trap concentrated layer comprising the steps of: providing a semi-insulating gallium arsenide substrate; forming a trap concentrated region in said substrate, said trap concentrated region being implanted with an electrically inactive impurity; forming a non-intentionally doped gallium arsenide buffer layer on said trap concentrated region of said substrate; forming a doped aluminum gallium arsenide layer on said buffer layer; and forming source, Schottky gate and drain contacts on the surface of the FET.
Claim 12
Independent Claim
82 words
A method of fabricating a MESFET having a high trap concentrated layer comprising the steps of: providing a semi-insulating gallium arsenide substrate; forming a trap concentrated region in said substrate, said trap concentrated region being implanted with an electrically inactive impurity; forming a non-intentionally doped gallium arsenide buffer layer on said trap concentrated region of said substrate; forming a doped aluminum gallium arsenide layer on said buffer layer; and forming source, Schottky gate and drain contacts on the surface of the FET.
Claim 13
Dependent Claim
19 words
The method of claim 9 wherein the trap concentrated region is implanted in one of blanket and selective form.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-25 | 1996-02-24 | 1996-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-25 | 2000-02-24 | 2000-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-25 | 2004-02-24 | 2004-08-25 | $7700.00 | Window Closed / Lapsed |